Based on FPGA multi channel charge signal acquisition module

1. DS18B20 should send a digital signal to the FPGA, so there is no need to do AD conversion. However, it may be serial data (I didn't read the data sheet of 18B20), and it may need to be converted in series and parallel inside the FPGA, and the amount of data of the general temperature sensor is not very large, so you can consider storing it in the BRAM inside the FPGA. There are many blocks of BRAM in the FPGA, and the writing of each channel of sensor data occupies a piece separately and needs to be controlled by a single-chip microcomputer.

2. When reading out, many data needs to be selected first, and the single-chip microcomputer selects a data to be sent to the serial port, and the serial port communicates with the PC. The serial port can be implemented inside the FPGA, and it is even simpler if the board has one.

3. It is estimated that the development board cannot be bought with DS18B20, but there should be one with a processor and serial port, and you can consult the FAE of the next supplier. Or look for it on Altera's ** yourself.

Your subject is actually quite simple.

The so-called acquisition system is to read the digital signal you want to collect (if the signal to be collected is analog, the ADC analog-to-digital conversion must be carried out first) by the FPGA, and then the FPGA controls it and stores it in the memory (here the SD card or flash memory chip is generally used).

Therefore, the whole system is actually composed of the following modules: ADC analog-to-digital conversion + core control module + memory (SD card or flash). The core control module consists of (:

Control of ADC sampling and memory. 2.Displays & Buttons:

It is mainly used for human-machine interface operation. ）

In fact, the display and buttons can not be loaded on the FPGA, or you can add a single-chip microcomputer to your circuit system, and the single-chip microcomputer will do human-computer interaction, and then send various commands to the FPGA in the form of instructions.

In fact, FPGA-based high-speed signal acquisition is almost always based on the same design principle. The ADC samples the signal, converts the analog signal into a digital signal, and then hands it over to the FPGA. At this time, the FPGA needs to write 3 IP modules:

IP core 1, state machine that controls ADC automatic high-speed conversion. Its function is to achieve high-speed 100M signal sampling, which is a cyclic timing control, so that after the ADC conversion is completed once, the FPGA reads out the data and hands the data to the second IP core (FIFO cache control IP), and then reads the second data immediately. However, it is necessary to pay attention to the selection of ADC chips, and the conversion rate must be higher than 100MHz.

IP core 2, FIFO cache control core: If you want to achieve high reliability and stability of collected data, FIFO is generally a must. The IP core of the FIFO determines whether the ADC has finished sampling at a time, and if so, stores the data in the FIFO buffer1.

Then, during the second sampling, the IP core 3 reads away the data of buffer 1 and then clears the data of buffer 1, and at the same time stores the sampled data read by the second time into buffer 2, and then the data of the second read is read away by IP core 3 from buffer 2, and the ADC samples the data and stores the data to buffer 1. (That is, the FIFO is divided into two buffers, one is always used to store the data converted by the ADC, and the other is used to allow the later function module to read out the last sampled data.) Both are simultaneous.

Buffer 1 and Buffer 2 work alternately. ）

IP Core 3: A functional module that processes digital signals. You mentioned that your task is ADC conversion, so IP core 3 you only need to alternately read the data from the two buffers of the FIFO.

1.Is there no need for a FIFO module at low speed?

Answer: In fact, FIFO can be saved whether it is high speed or low speed, but for the stability of the system and the stability of the sampling rate, and the high reliability of the collected data, the FIFO buffer is added.

2.What should be paid attention to in high-speed signal PCB wiring?

A: 1Power filtering must be done well, otherwise there will be ripple.

2.All lines of the positive power supply (VCC) are best sandwiched between them with two ground wires (GND) (this can be ignored if the entire board is copper-poured).

3.The double-sided panel needs to have the front and back traces perpendicular to reduce EMC.

4.Analog and digital power are separated, as is ground. The digital and analog power supplies on the entire board are connected with two 0 ohm resistors. (1 power positive, 1 ground).

5.It is better to pour copper.