What is an IP core? What are IP cores?

In the reusable design methodology of integrated circuits, IP core, the full name of intellectual property core, refers to the reusable module provided by a certain party in the form of logic unit and chip design. IP cores have usually passed the design verification, and the designer Hongnaite designs based on the IP core, which can shorten the cycle required for the design.

IP cores can be provided by one party to the other by agreement, or possessed by one party alone. The concept of IP core is derived from the patent certificate of product design and the copyright of the source. Designers can use the IP core as the basis for logic design of ASIC or field-programmable gate arrays to reduce design cycles.

IP cores are divided into soft cores, hard cores, and solid cores. Soft cores are typically process-agnostic designs with register-level hardware description language descriptions** that can be subsequently designed; The hard core is a series of process documents after the former is synthesized, laid out and routed through logic, and has a specific process form and physical implementation; The fixed kernel is usually somewhere in between, and it has been obtained by designers in the form of logical gate-level netlists through functional verification, timing analysis, and other processes.

There are three types of IP cores.

There are three different forms of existence of IP cores: HDL language form, netlist form, and layout form. They correspond to the three types of IP cores we often say:

Softcore, solid, and hardcore. This categorization is based on how the product is delivered, and each of the three IP core implementations has its own unique characteristics. The solid core is a compromise between the soft core and the hard core.

Most of the IP cores used in FPGAs are softcores, which help users adjust parameters and enhance reusability. Soft cores are usually provided in encrypted form, so that the actual RTL is invisible to the user, but the layout and cabling are flexible. In these encrypted soft cores, if the kernel is parameterized, the parameters can be easily manipulated by the user via header files or a graphical user interface (GUI).

For cores with strict timing requirements, such as PCI interface cores, specific signals can be pre-wired or specific cabling resources can be allocated to meet timing requirements. These cores can be classified as solid cores, and since the cores are pre-designed modules, this has the potential to affect the overall design that contains the core. Since the setup, hold-up time, and handshake signals of the kernel can all be fixed, other circuits must be designed to properly interface with the kernel.

If the core has a fixed layout or a partially fixed layout, then this will also affect the layout of the other circuits.

1. Whether the IP core is a hard core or a solid core.

2. If an FPGA is loaded with ARM cores, network port cores, DDR2 control cores, and serial port cores, what is the difference between it and an ARM chip with the same module function?

3. If an FPGA is loaded with the DSP core of STM32VC5416 (assuming it can), then whether the assembly** running on the 5416 can also run on the FPGA, and whether the efficiency is the same.

1. IP cores are divided into three categories: hard core, solid core, and soft core.

Hardcore: Layout-level IP, such as FPGA's on-chip ARM, Xilinx's MIG (DDR controller).

Solid core: Netlist-level IP, most of which are provided by market vendors, are generated graphically, such as Altera Nios II

Soft core: **-level IP, most of these IPs are open source IPs on the Internet, and the source can be directly seen **(..)v or .hdl)

2. There is not much difference in function. However, FPGAs are highly flexible, but of course, the cost is not the same as the difficulty of development.

3. FPGA does not have the DSP core you are talking about, the reason: the processing power of FPGA is much stronger than that of DSP, and the comparison rate is different, and different FPGAs will be different.

The IP (Intellectual Property) core designs some of the more complex function blocks commonly used in digital circuits, such as FIR filters, SDRAM controllers, PCI interfaces, etc., into modules that can modify parameters. As CPLD FPGAs grow in size and design complexity (IC complexity increases by 55% per year, while design capability only increases by 21% per year), the primary task of the designer is to complete the complex design within the specified time frame. The use of IP cores is a trend to avoid duplication of effort and greatly reduce the burden on engineers, and the reuse of IP cores greatly reduces the time to market.

The use of IP cores to design electronic systems is easy to refer to and easy to modify the functions of basic components. IP cores with complex functions and commercial value generally have intellectual property rights, although the market activities of IP cores are not standardized, there are still many integrated circuit design companies engaged in the design, development and marketing of IP cores.