Questions about differential IO vs. single ended IO of the spartan 3E FPGA

1. Except for a few IO ports on the development board, such as PROG and JTAG, they are all general-purpose IO ports, which means that they can be set as ordinary IOs, or they can be configured as differential ports by the development software pin constraints.

2. This should be measured with a multimeter to see its voltage, generally high level means 1, 0V means logic 0. Another simple way is to set the output port to LED light, use the light to check whether the output is normal, if the output is 1, then the light is on to indicate that there is no problem.

Practice on your own.

The first question means that the FPGA needs to be configured on the hardware to make it work, such as the power supply, which must be given according to the requirements, and it depends on whether the series you choose has special pins that need to be assigned.

The second is most likely caused by the first problem, and the hardware can be guaranteed to be correct before proceeding to the next step.

Your problem shouldn't be big, just learn slowly.

1.I don't know which version of ise you're using. The latest ISE calls the Planahead environment, which constrains the pins.

When a pair is a differential line, select both pins at the same time under the IO constraint window, right-click, and select "Make Differential", and the differential pair is constrained. It can also be implemented by directly calling the differential primitive in **. By default, they are all single-ended;After the pin constraint is completed, a DRC check can be done to check the basic errors that do not meet the requirements of the device

2.Let's make sure your constraint is successful

1. For the bank transmitted as LVDS, it must be connected to VCCIO.

2. The LVDS of the left and right banks (i.e., 1 2 5 6 bank) does not need external matching resistors to send differential pair signals, and the upper and lower banks (i.e. 3 4 7 8 banks) do.

Two are the points that need to be paid attention to in PCB design.

3. When assigning pins, the LVDS differential signal of the left and right banks is selected as LVDS as the IO standard when IO is allocatedThe LVDS differential signal of the upper and lower banks is selected as LVDS E 3R when the IO is assigned.

4. When assigning pins, as long as the P terminal (+) of the LVDS signal is specified, the N terminal (-) will be automatically matchedIn fact, only one signal interface is required in Verilog, and there is no need for a differential pair interface to be defined in the source **.

The MegaWizard Plug-InManager manager of the Quartus II software provides IP cores for LVDS signal processing, including LVDS transmit cores (AltLVDS TX) and LVDS receive cores (ALTLVDS RX).

LVDS transmit core (altlvds tx): Serializes a parallel signal into an LVDS signal and transmits it.

LVDS Receiver Core (AltLVDS RX): Receives the LVDS serial signal and parallelizes this signal, i.e., a deserializer.

Receive the nucleus with LVDS (Altlvds RX).

If you can add it, you can add 245, and you can't add an example.

This line is not easy to find. You can do it with networking.

I looked at it as if it meant that there was a synchronous set.

Typical reset signals are asynchronous. Synchronous resets are rarely used. If you really want to reset synchronously, then don't worry about this warn. Maybe your original meaning was also an asynchronous reset, but your ** was written incorrectly.

A typical synchronous reset is when there is no reset in the sensitive variable of the process.

There are some common steps to keep in mind when assigning signals to the IO pins:

1.Use a single spreadsheet to list all planned signal assignments, along with their important attributes such as IO standards, voltages, required termination methods, and associated clocks. Gear up.

2.Check the manufacturer's block regional compatibility guidelines.

3.Consider using a second spreadsheet to lay out the FPGA to determine which pins are generic, which are dedicated, which support differential signal pairs and global and local clocks, and which require reference voltages.

4.Using the information and zone compatibility guidelines of the above two spreadsheets, the most restricted signal is assigned to the pin first, and the least restricted signal is assigned last. For example, you may want to assign serial buses and clock signals first, as they are usually only assigned to a few specific pins.

5.Redistribute signal buses to the extent they are restricted. At this stage, it may be necessary to carefully weigh design issues such as simultaneous switching outputs (SSOs) and incompatibility with the IO standard, especially if you have many high-speed outputs or use several different IO standards.

If your design requires a local area clock, you may need to use pins near the high-speed bus, and it's a good idea to keep this requirement in mind in advance so that you don't end up with the most appropriate pins for it. If the IO standard selected for a particular block requires a reference to the silver voltage signal, remember not to assign these pins yet. Differential signals are always assigned before single-ended signals.

If an FPGA provides on-chip pulsation termination, then it may also apply to other compatibility rules.

6.Distribute the remaining signals in the right places.

At this stage, consider writing an HDL file that contains only port assignments. Then add the necessary supporting information for IO standards and SSOs, etc., by manually creating a restriction file using the tools provided by the vendor or using a texter. Once you have these basic files ready, you can run the place-and-route tool to see if you have overlooked some guidelines or made a wrong assignment.

The logical resources are different, and the pin seems to be basically compatible.