Problems in the I2C bus protocol in microcontrollers

scl=0;Pull down the clock line and prepare to receive the data, otherwise you won't be able to make the first rising edge in the later loop.

delay();Delay.

sda=1;Release the data line (not driven, hovering) and the sender drives this line.

delay();Delay.

for(i=0;i<8;i++) 8 cycles to receive 1 bit each time.

scl=1;Pull up the clock line, make a rising edge, read the data, and the sender will keep the data on the SDA line.

delay();

k=(k<<1)|sda;The other bits of k are shifted to the left, saving the state of the data line at the lowest bit of k.

scl=0;Pull down the clock line and wait for the send to put down 1 bit on the data cable.

delay();

scl=0;According to the protocol, when the SCL is 1 during read and write, the SDA data is not allowed to change (in this case, it is pulled down because the host is ready to release the bus).

delay();

sda=1;The master releases the bus (if SDA = 0 and the master does not pull the SDA up, the slave cannot pull up the SDA at this time, that is to say, the slave sends 1 in this case, but the master receives 0.)）

delay();

If there is any error, please correct it.

In order to prepare for reading the data, first pull the clock line low. The data cable is set to the input state.

I2C is mainly used in chip communication.

1. First of all, the relationship between the master and the slave should be distinguished by the IIC communication, when the master writes to the slave, the single-chip microcomputer generally enters the detection and response signal state after transmitting a data: first set the two pins to SDA=1;scl=1；Then keep checking the level status of the SDA pin for a certain period of time, for example, if you make a loop for(i=255; i>0;i--) is constantly judged, when the level of SDA is low, it jumps out of the loop, indicating that the slave has ACK at this time, which can indicate that the I2C device is pulling down; If it is high, it will always judge the whole cycle, and when it is still high at the end, it means that there is no response.

2. There is definitely a difference between writing a response and reading a response. Write reply is when you receive a data during you read the slave data, you can reply (answer if you want to continue communication), reset (pull down), and set the position if you don't want to answer (when you want to end communication) (SDA=1). During the read response when the master writes data to the slave, the slave will reply whenever it receives a data (pull the data SDA line down), and the master will continue to detect the level of the SDA line, and the master will know whether the slave has correctly received the data sent by the master by the level of the SDA.

The data transmission must be responsive, and the associated response clock pulses are generated by the host. During the clock pulse in response, the transmitter releases the SDA line (high).

During the responding clock pulse, the receiver must pull the SDA line low so that it stays stable low during the high levels of this clock pulse.

A receiver that is normally addressed must produce a response after each byte received, in addition to the data that starts with the CBUS address. When the slave fails to respond to the slave address (for example, it is executing some real-time function and cannot receive or send), the slave must keep the data line high, and the master then generates a stop hungry condition to terminate the transmission or a repeat start condition to start a new transmission.

If the slave receiver responds with the slave address, but cannot receive more data bytes after a period of transmission, the master must terminate the transmission again. This is represented by the fact that the slave does not produce a response after the first byte. The slave keeps the data line high, and the master produces a stop or repeat start condition.

If there is a master receiver in the transmission, it must notify the slave sender of the end of the data by producing a response when the last byte is emitted by the slave. The slave transmitter must release the data line, allowing the master to generate a stop or repeat start condition. All hosts generate their own clocks on the SCL line to transmit messages on the I2C bus.

The data is only valid for the high cycles of the clock, so a deterministic clock is required for bitwise arbitration.

Clock synchronization is performed via a wire and an I2C interface connected to an SCL line. This means that switching the high to low of the SCL line causes the device to start counting their low cycles, and once the clock of the device goes low, it keeps the SCL line in that state until it reaches the high level of the clock. But if another clock is still on a low cycle, the low-to-high switch of this clock will not change the state of the SCL line.

As a result, the SCL line is kept low by the device with the longest low period. Devices with short periods of low levels during this flutter infiltration will enter a wait-high state.

When all the devices involved have completed their low periods, the clock line is released and goes high. After that, there is no difference between the state of the device clock and the SCL line, and all devices will start counting their high-level cycles. The device that completes the high cycle first pulls the SCL line low again.

The resulting synchronous SCL clock has a low period determined by the device with the longest clock period at the low level, and a spine high period determined by the device with the shortest clock period at the high level.

It is a bus that includes two wires: a data line SDA and a clock line SCL.

Through this bus, the single-chip microcomputer communicates with each external chip.

If you want to transmit one byte of data, you must transmit it bit by bit on the data line SDA;

For each transmitted bit, a pulse is output on the clock line SCL.

There are also "start", "end" and "answer" bits, which can be understood by looking at the sequence diagram.

On the bus, multiple devices can be attached, which has the problem of "slave address";

Inside a device, there may be multiple memory cells, which brings us to the problem of "word addresses".

The I2C bus is indeed very wordy.

Communication lines, clock and data lines between master and slave.

One is the data line SDA, the other is the debugging clock line SCL, and the single-chip microcomputer is more timing-series to judge the accepted data. Just read the timing diagram.

A non-response means that the SDA is high.

The point of I2C transmission is that one byte is transmitted and one byte is followed by another"Response"Signal.

This response signal may come from the master or the slave, and the specific person depends on the direction of transmission.

Hereafter, as I am accustomed to call it"No response":

There are two types of transmission directions (each case has two possibilities: A has no answer and B has a response).

1.Host-> slave, after the master sends a byte to the slave, the master reads the slave's response signal (the master reads the SDA line).

a) If the master reads the SDA high, the slave has no answer.

b) The master reads the SDA as low, indicating that the slave has an answer.

2.Slave-> master, after the master reads a byte from the slave, the master sends a response signal to the slave (the master writes the SDA line).

a) The master writes SDA to a high level, and after the slave receives the no answer signal from the master, the slave stops transmitting and waits for the stop signal of the master.

b) The master writes SDA low, and the slave continues to output the next byte after receiving the response signal from the master.

The I2C bus (Inter-IC bus) is a bidirectional, two-wire continuous bus that provides communication lines between integrated circuits (ICS). The I2C bus is a serial extension technology that was first introduced by Philips and is widely used in televisions, video recorders, and audio equipment. I2C bus means "a specification or protocol that accomplishes the exchange of information between integrated circuits or functional units".

The I2C bus launched by Philips uses a data line (SDA) and a clock line (SCL) to complete the data transmission and the expansion of peripheral devices. The addressing of each node is a soft addressing mode, which saves the chip selection line, and the standard addressing byte SLAM is 7 bits, which can address 127 units. The I2C bus has three data transfer speeds: standard, fast mode and high-speed mode.

The standard mode is 100kbps, the fast mode is 400kbps, and the high-speed mode supports fast speeds. All modes are compatible with the next highest transfer speed. The I2C bus supports both 7-bit and 10-bit address space devices and devices operating at different voltages.

The I2C (Inter Integrated Circuit) bus is a two-wire serial bus developed by Philips to connect microcontrollers and their peripherals. It is a bus standard widely used in the field of microelectronic communication control. It is a special form of synchronous communication, which has the advantages of fewer interface lines, simple control mode, small device packaging form, and high communication rate.

The I2C bus supports any IC production process (CMOS, bipolar). Information is passed between devices connected to the bus via serial data (SDA) and serial clock (SCL) lines. Each device has a unique address identifier (whether a microcontroller – MCU, LCD drive, memory, or keyboard interface) and can act as a transmitter or receiver (depending on the device's functionality).

An LCD drive can only act as a receiver, while a memory can both receive and send data. In addition to the transmitter and receiver, the device can also be considered as a master or slave when performing data transmission (see Table 1). A master is a device that initializes the data transmission of the bus and generates a clock signal that allows it to be transmitted.

At this point, any device that is addressed is considered a slave.