Q The principle of the watchdog microcontroller, what is the watchdog in the microcontroller, and wh

The working principle of the watchdog: after the system runs, the watchdog counter is started, and the watchdog begins to count automatically, if the watchdog is not cleared at a certain time, then the watchdog counter will overflow and cause the watchdog to be interrupted, causing the system to reset. The role of the watchdog is to prevent the program from looping, or running away.

In instrumentation programs, there are generally watchdogs.

Watchdog (WDT) is a timer, after turning on the watchdog timer (such as timing 200ms), in the MCU program every certain time (less than 200ms) to "feed the dog", that is, the watchdog timer is cleared.

Watchdogs are divided into hardware watchdogs and software watchdogs. The hardware watchdog is the use of a timer circuit, its timing output is connected to the reset end of the circuit, the program in a certain time range to zero the timer (commonly known as "feeding the dog"), so when the program is working normally, the timer can not overflow, and can not produce a reset signal.

If the program fails and the watchdog is not reset within the timing period, the watchdog timer overflows to generate a reset signal and restart the system. The software watchdog is the same in principle, except that the timer on the hardware circuit is replaced by the internal timer of the processor, which can simplify the hardware circuit design, but it is not as good as the hardware timer in terms of reliability.

For example, if the system's internal timer itself fails, it cannot be detected. Of course, there are also dual timers that monitor each other, which not only increases the overhead of the system, but also does not solve all the problems, such as interrupting the system and causing the timer to fail due to a failure.

How the watchdog program works:

1. The watchdog is a counter that counts the pulses provided by an independent clock source without any external components;

2. The independent RC clock signal source refers to the separation of the RC oscillator and the external RC oscillator of the OSC1 pin, and the MCU system clock composed of the OSC1 and OSC2 external crystal oscillators or ceramic resonators is separated, which means that even if the MCU enters the sleep state of the system clock stop, the monitoring timer can still run;

3. During the execution of the program of the single-chip microcomputer, a watchdog timer timeout overflow will make the single-chip microcomputer produce a reset operation, if the single-chip microcomputer is in a sleep state, a watchdog timer timeout overflow will make the single-chip microcomputer be woken up, restore the normal operation state, and continue to execute the program that was put on hold before entering sleep;

4. Every time the watchdog timer times out, the t0 bit in the state condition register will be cleared to 0, so as to record the watchdog overflow event that has occurred in the past for program query and judgment;

5. When the watchdog timer is equal to 0, the watchdog timer will be permanently disabled, and when the watchdog timer is equal to 1, the watchdog timer will be permanently enabled by the lease.

How the watchdog program works:

1. The watchdog is a counter that counts the pulses provided by an independent clock source without any external components;

2. The independent RC clock signal source refers to the separation of the RC oscillator and the external RC oscillator of the OSC1 pin, and the MCU system clock composed of the OSC1 and OSC2 external crystal oscillators or ceramic resonators is separated, which means that even if the MCU enters the sleep state of the system clock stop, the monitoring timer can still run;

3. During the execution of the program of the single-trace old film search machine, a watchdog timer timeout overflow will make the single-chip microcomputer produce a reset operation, if the single-chip microcomputer is in a sleep state, a watchdog timer timer overflow will make the single-piece posture calendar machine be woken up, restore the normal operation state of the punch, and continue to execute the program that was shelved before entering sleep;

4. Every time the watchdog timer times out, the t0 bit in the state condition register will be cleared to 0, so as to record the watchdog overflow event that has occurred in the past for program query and judgment;

5. When the watchdog timer is equal to 0, the watchdog timer will be permanently disabled, and when the watchdog timer is equal to 1, the watchdog timer will be permanently enabled.