What s going on with I2C transferring data?

To learn I2C communication well, you must understand the I2C communication protocol, that is, to implement the rules formulated, the timing can be written by yourself, as long as the conditions are met, after the start signal, if you write data, you must send the data through the SDA line, the signal changes on the SDA are changed during the SCL low level, the signal on the SDA is guaranteed to be stable during the high level of the SCL, and the general read data is read and written during the high level of the SCL.

The I2C (Inter Integrated Circuit) bus is a two-wire serial bus developed by Philips to connect microcontrollers and their peripherals.

About I2C:

It is a bus standard widely used in the field of microelectronic communication control. It is a special form of synchronous communication, which has the advantages of fewer interface lines, simple control mode, small device packaging form, and high communication rate. The I2C bus supports any IC production process (CMOS, bipolar).

Information is passed between devices connected to the bus via serial data (SDA) and serial clock (SCL) lines. Each device has a unique address identifier (whether a microcontroller – MCU, LCD drive, memory, or keyboard interface) and can act as a transmitter or receiver (depending on the device's functionality). An LCD drive can only act as a receiver, while a memory can both receive and send data.

In addition to the transmitter and receiver, the device can also be considered as a master or slave when performing data transmission (see Table 1). A master is a device that initializes the data transmission of the bus and generates a clock signal that allows it to be transmitted. At this point, any device that is addressed is considered a slave.

The data transmission must be responsive, and the associated response clock pulses are generated by the host. During the clock pulse in response, the transmitter releases the SDA line (high).

During the responding clock pulse, the receiver must pull the SDA line low so that it stays stable low during the high levels of this clock pulse.

A receiver that is normally addressed must produce a response after each byte received, in addition to the data that starts with the CBUS address. When the slave fails to respond to the slave address (for example, it is executing some real-time function and cannot receive or send), the slave must keep the data line high, and the master then generates a stop hungry condition to terminate the transmission or a repeat start condition to start a new transmission.

If the slave receiver responds with the slave address, but cannot receive more data bytes after a period of transmission, the master must terminate the transmission again. This is represented by the fact that the slave does not produce a response after the first byte. The slave keeps the data line high, and the master produces a stop or repeat start condition.

If there is a master receiver in the transmission, it must notify the slave sender of the end of the data by producing a response when the last byte is emitted by the slave. The slave transmitter must release the data line, allowing the master to generate a stop or repeat start condition. All hosts generate their own clocks on the SCL line to transmit messages on the I2C bus.

The data is only valid for the high cycles of the clock, so a deterministic clock is required for bitwise arbitration.

Clock synchronization is performed via a wire and an I2C interface connected to an SCL line. This means that switching the high to low of the SCL line causes the device to start counting their low cycles, and once the clock of the device goes low, it keeps the SCL line in that state until it reaches the high level of the clock. But if another clock is still on a low cycle, the low-to-high switch of this clock will not change the state of the SCL line.

As a result, the SCL line is kept low by the device with the longest low period. Devices with short periods of low levels during this flutter infiltration will enter a wait-high state.

When all the devices involved have completed their low periods, the clock line is released and goes high. After that, there is no difference between the state of the device clock and the SCL line, and all devices will start counting their high-level cycles. The device that completes the high cycle first pulls the SCL line low again.

The resulting synchronous SCL clock has a low period determined by the device with the longest clock period at the low level, and a spine high period determined by the device with the shortest clock period at the high level.

0.Unable to transmit: shake a few times and it's good > whether it is a problem of poor contact, first find a way to confirm that there is no bad contact.

3.Interference question: You mentioned that the test passed, can the test environment be shaken at the same distance? Then in the actual environment, whether the wire can be shortened, and then shake it to try.

In this case, the main device can only try a few more times, how can it get stuck with the master? If the communication is stuck due to constant attempts, the root cause is the hardware connection and interference. Is there any evidence that the communication is blocked due to repeated attempts?

1.Card owner: Does the master and slave devices have to have timeout processing to deal with the card owner's problem?

The real problem doesn't seem to have arisen yet, can you find out more about it? Then we will consider specific solutions.

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The SDA bus is a two-way data line, which is the I O pin of the single-chip microcomputer, and the output of the single-chip microcomputer is the single-chip microcomputer to control the level of the SDA. However, when reading data, i.e. microcontroller input, the data is sent from the I2C device. If SDA=0 before the read, that is, if it is not pulled up, the SDA line will remain low and will be pulled low.

No matter what data i2C sends, it is 0, that is, the microcontroller can only read all 0.

Therefore, it must be pulled up first, so that the SDA bus can be controlled by the I2C device, send data, and the microcontroller can read the correct data.

The I2C bus is a kind of serial bus launched by Phlips, and the I2C bus has only two bidirectional signal lines. One of them is the sedentical line SDA, and the other is the clock line SCL.

1) Basic process:

1.The host signals the start.

2.The master then sends a one-byte slave address information, in which the lowest bit is the read-write control code (1 is read, 0 is write), and the highest seven bits are the slave address.

3.The slave sends out an approval signal.

4.The master starts to send signals, and after each byte is sent, the slave sends an approval signal to the host.

5.The host sends out a stop signal.

Due to the different kinds of processes (CMOS, NMOS, PMOS, bipolar) of the devices connected to the I2C bus, the levels of logic 0 (low) and logic 1 (high) are not fixed, they are determined by the relevant level of the supply VCC, and a clock pulse is generated for each data bit transmitted. When the SCL line is high, the SDA line switches from high to low, which indicates the starting condition of the group backup.

When the SCL line is high, the SDA line switches from low to high, which indicates the stop of the branch or group.

The start and stop conditions are generally generated by the host, with the bus being considered busy after the start condition and the bus being idle again after a certain period of time after the stop condition.

If a repeat start condition is generated without a stop condition, the bus will remain busy, and the start condition (S) and the repeat start condition (SR) are functionally the same.