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Anonymous users2024-02-13There should be another step before the procedure is z=5, or z=10, etc., or z-equals some other number.
If Z=10, then the actual address of y0z0 is y10, and if z=20, then the actual address of y10z0 is 10+20=30
This is explained in detail in Mitsubishi's manual.
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Anonymous users2024-02-12The application of Mitsubishi PLC's metamorphic register is actually a kind of instruction configuration, and K2Y0Z0 can be decomposed into K2Y0 and Y0Z0 to understand. K2Y0 is a configuration of "tag number + initial number of bit soft components", K2Y0 refers to 8 points from Y0 to Y7 is specified (K1Y0 refers to 4 points from Y0 to Y3 are specified); Y0Z0 means that the soft component used will change to "directly specified soft component number + address register content", when Z0=3, Y0Z0=Y(0+3)=Y3, Y3 becomes the specified soft component.
When z0=3 and xy is a hexadecimal number, k2y0z0=k2y(0+3)=k2y3=8 points from y3 to ya are specified;
When z0=20 (20 is converted to hexadecimal=14), xy is a hexadecimal number, y-64 points, k2y0z0=k2y(0+14)=k2yd=8 points from yd to y14 are specified;
When z0=20 and xy is a hexadecimal number, k2d0z0=k2d(0+20)=k2d20=8 points from d20 to d27 are specified.
The Mitsubishi Q-Series Programming Manual has detailed instructions on command configuration.
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Anonymous users2024-02-11The SHRB instruction for register shift in the PLC moves the data value into the shift register. In the ladder diagram, en is the enable input, and the shift pulse signal is connected, and each time the enable is active, the entire shift register moves by 1 bit.
data is the data input terminal, which is connected to the binary value moved into the shift register, and the value of the bit is moved into the register when the instruction is executed. s bit specifies the lowest bit of the shift register. n specifies the length and direction of the shift register, and the maximum length of the shift register is 64 bits.
A positive value indicates a left shift, where the input data (data) is moved into the lowest bit of the shift register (S bit) and out of the highest bit of the shift register. The evicted data is placed in the overflow memory bit (. A negative value of n indicates a right shift, where the input data is moved into the highest bit of the shift register and out of the lowest bit (s bit).
The removed data item is late placed in the overflow memory bit (.
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Anonymous users2024-02-10Variable address registers refer to the registers ESI, EDI, SI and DI, which are mainly used to store the rotten line offset of the storage unit in the segment.
Data registers.
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There are registers in the CPU, such as the accumulator in the ALU (Computing Unit). When the CPU operates on these registers, it also needs to have an address in order to distinguish between different registers. This address is the address code you are talking about.
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