What is the address encoding of registers in the CPU?

There are registers in the CPU, such as the accumulator in the ALU (Computing Unit). When the CPU operates on these registers, it also needs to have an address in order to distinguish between different registers. This address is the address code you are talking about.

Register components, including general-purpose registers, specialized registers, and control registers.

The general registers of 32-bit CPUs can be divided into two types: fixed-point and floating-point, which are used to store the register operands and operation results in the instruction.

General-purpose registers are an important part of the processor, and most instructions need to access them. The width of the general-purpose register determines the width of the data path inside the computer, and the number of ports can often affect the parallelism of the internal operation.

Dedicated registers are registers that are needed to perform some special operations.

Control registers are usually used to indicate the state of machine execution, or to maintain certain pointers, such as processing status registers, base address registers for address translation directories, privileged state registers, condition code registers, abnormal event handling registers, and error detection registers.

Sometimes, there are some caches in the processor, which are used to temporarily store some data instructions, the larger the cache, the faster the CPU computing speed, the current high-end processors on the market have a L2 cache of about 2M, and the high-end processors have a L2 cache of about 4M.

The length of the CPU and general registers is determined by the word length of the machine, which is convenient for operation control. General-purpose registers can be used to transfer and stage data, as well as participate in arithmetic logic operations and save the results of calculations. In addition to that, they also have some special features in their own right.

The length of common registers depends on the machine word length, and assembly language programmers must be familiar with the general and special uses of each register in order to use them correctly and sensibly in their programs.

General-purpose registers can be used to transfer and stage data, as well as participate in arithmetic logic operations and save the results of calculations. In addition to that, they also have some special features in their own right. Assembly language programmers must be familiar with the general and special uses of each register in order to use them correctly and rationally in the program.

Damn, this CPU manufacturer decides when it is produced, just like what model of your CPU is decided when it leaves the factory.

Answer]:B In order to ensure that the program can be executed continuously, the CPU must have some means to determine the address of the next search order. This is what the program counter does, so it is often called the program counter.

When a program is transferred, the end result of the transfer instruction execution is to change the value of the PC, which is the address of the next instruction to be executed. In some machines, it is also called the PC as the instruction pointer fiber lp.

There are 8 general-purpose registers in the CPU: AX, BX, CX, DX, SP, BP, SI, DI; Two control registers IP, FL; The four segment registers CS, DS, SS, and the general registers can all be used to temporarily store data or intermediate results for participating calculations, but they have their own special purposes. For example, AX is dedicated to the accumulator, and some instructions specify that it is used to store operands and operation results; cx is a counter register, which is used as a counter in some instructions; dx is the data register; bx is the base address register, bp is the base address pointer, si is the source address change register, and di is the destination address change register, these four registers are used to store the intra-segment offset address (valid address) or part of the intra-segment offset address in data addressing; sp is a stack indicator, which is used to store valid addresses at the top of the stack. Two control registers are used to store relevant status and control information.

For example, the flag register FL is used to store status flags and control flags; The instruction pointer is used to store the valid address of the next instruction to be retrieved. Four segment registers are used to store segment addresses. For example, the cs register is used to store the segment address of the ** segment; The DS register is used to store the segment address of the data segment; The SS register is used to store the segment address of the stack segment; The ES register is used to store the segment address of the extended segment.

I'm talking about 8086, 32 bits are more complicated. I think theoretically there should only be CS and IP, which are the two registers associated with executing instructions, which always store the address of the next instruction. SS and SP shouldn't always be used to store addresses, and I think of a special case.

ss,sp is stack-related registers, the cpu will think that ss:sp points to the top of the stack, but for example, if you write a subroutine, store the values of these two registers at the beginning, and then use it as a general register, as long as you do not have a stack out of the stack in the program, and restore the value of ss,sp at the end, the whole program is still fine, although generally no one is so painful, but I think this can show that ss,sp may not always store the address. Only CS and IP always store the address.

Data registers are mainly used to store information such as operands and operation results, so as to save the time required to read operands and occupy the bus and access memory.

The 32-bit CPU has four 32-bit general-purpose registers EAX, EBX, ECX, and EDX. Access to the lower 16-bit data does not affect the higher 16-bit data. These low 16-bit registers are named as:

AX, BX, CX, and DX, which are consistent with the registers in the previous CPU.

The four 16-bit registers can be split into eight independent 8-bit registers (ax:ah-al, bx:bh-bl, cx:).

ch-cl, dx:dh-dl), each register has its own name and can be accessed independently. Programmers can take advantage of this "separable" nature of data registers to flexibly process byte information.

Registers AX and AL are often referred to as accumulators, and operations with accumulators can take less time. Accumulators can be used for operations such as multiplication, division, input and output, and they are used frequently;

The register bx is called the base register. It can be used as a memory pointer;

The register CX is called the Count Register. When looping and string operations, use it to control the number of loops; In the bit operation, when shifting multiple digits, CL should be used to indicate the number of shifted bits;

The register DX is called the data register. It can be used as the default operand for multiplication and division, and can also be used to store the port address of Io.

In a 16-bit CPU, AX, BX, CX, and DX cannot be used as base address and address change registers to store the address of the memory cell, but in a 32-bit CPU, the 32-bit registers EAX, EBX, ECX, and EDX can not only transmit data, save arithmetic logic results, but also serve as pointer registers, so these 32-bit registers are more versatile. For more information, see Section - Addressing Methods for 32-Digit Addresses.

A 32-bit CPU expands the instruction pointer to 32 bits and denotes it as EIP, with the lower 16 bits of the EIP doing the same thing as the IP in the previous CPU.

The instruction pointer EIP and IP (Instruction Pointer) are the offsets in the ** section of the instruction that will be executed next time. Used to provide the address of the instruction in memory. In systems with prefetching instructions, the next order to be executed is usually prefetched to the instruction queue unless a transfer occurs.

Therefore, the existence of a queue of instructions is not taken into account when understanding their function.

In the real mode, since the maximum range of each segment is 64K, the top 16 bits in the EIP must be 0, which is equivalent to using only the IP of the lower 16 bits to reflect the execution order of the instructions in the program.

The 32-bit CPU has 2 32-bit general-purpose registers, ESI and EDI. The lower 16 bits correspond to the SI and DI in the previous CPU, and the access to the lower 16 bits does not affect the upper 16 bits of data.

The registers ESI, EDI, SI, and DI are called index registers, which are mainly used to store the offset of the memory cell in the segment, and use them to realize the addressing of multiple memory operands (described in detail in Chapter 3) to facilitate access to the memory cell in different address forms.

Address change registers are not divisible into 8-bit registers. As a general-purpose register, it can also store operands and results of arithmetic logic operations.

They can be used as general memory pointers. During the execution of string manipulation instructions, they have specific requirements and special functions. See section for a detailed description.