The difference between tasks and functions in the verilog language

Verilog HDL is a hardware description language (HDL) that describes the structure and behavior of digital system hardware in text form, and can be used to represent logic circuit diagrams, logical expressions, and logical functions completed by digital logic systems.

Features: Verilog is designed to be a hardware description language with a basic syntax similar to that of C. This is because C has been widely used in many fields since the design of Verilog, and many of the linguistic elements of C have been used to by many people.

A hardware description language similar to C that can be easier for circuit designers to learn and accept. However, there are many differences between Verilog and C. In addition, as a hardware description language that is different from ordinary computer programming languages, it also has some unique language elements, such as line nets and registers in the form of vectors, non-blocking assignments in the process, etc.

Overall, designers with C will be able to quickly master the Verilog hardware description language.

The biggest feature of Verilog HDL is that it is easy to learn and use, if you have programming experience in C language, you can quickly learn and master it in a short period of time, so you can arrange Verilog HDL content in related courses related to ASIC design to teach, because the HDL language itself is specifically oriented to hardware and system design, such an arrangement can enable learners to gain experience in designing actual circuits at the same time. In comparison, VHDL is a bit more difficult to learn. However, it is important to note that Verilog HDL's freer syntax also makes beginners make some mistakes.

For the companies that can be reached in China, it should be more in the verilog language than in the vhdl language.

This assignment statement is mainly composed of the concatenation operator {}, the repeat operator }, and bitselection. The specific meaning of this assignment statement is:

The 11th bit of h11 a re (0 or 1) and h11 a re (itself), and the 4 bits of 0 (0000) are concatenated together to form a number plus the following part, where } is made up of the repeat operator}, i.e. there are 3 bits. To understand this, it is easy to understand as long as you combine the splice operator and the repeat operator and bit selection. Here's an example:

Define wire [15:0] h11 a re = 16'b1010_0111_1011_0000;The 15th position h11 a re[15] = 1, and the 11th position h11 a re[11] = 0;

wire a = 3'b101; wire b = 2'b01;That is, the splicing of a and b is equal to = 5'b10101;i.e. = 6'b010101; Repeat operator } = = 4'b0101;It's quite the same as copying. It's no problem to understand these 3 and look at the above.

Always is not next to a cluster of loops, always is a process block. always@ (a or b or c) We can often see the always statement such as the above sentence, when the a, b or c signal in parentheses changes, the always module is activated, and the statement in the module can be executed. The signals in parentheses are called the list of sensitive signals.

All the always-blocks have a parallel relationship with each other, and who is first and who is last does not affect the order of execution.

for is a circular statement, but it cannot be synthesized (compiled). for is usually used in test files. Or it can be used to attach an initial value to the RAM. For example, a RAM space is defined.

reg [n-1:0] mem [word-1:0];

You can use a for loop when initializing the early oak.

integer i;

for(i=0;In this way, all the contents of RAM are defined as 0. However, for cannot be used in circuit entities.

Verilog is a hardware description language, used to describe the structure and behavior of hardware, not software, not C, very different, there is no such thing as loops. It can be said that the program made by verilog is actually the same thing as the drawing of hardware engineers, each statement, each module, represents the use of a chip, and then connected to the line so that the hardware circuit comes from the loop, pay attention to the good difference.