Why are FPGAs struggling to handle complex packets?

1.First of all, "the performance of processing things like IP fragment reorganization, decompression, and packet sequencing is very low", I don't think so.

2.Look at the CPU operation, it has to go through several processes such as fetching instructions, fetching data, executing instructions, and these processes are also completed by using hardware, so in essence, the execution of software is also the result of the operation of hardware circuits.

3.Some people think that CPUs are fast and therefore have higher performance than FPGAs. In fact, the advantage of FPGA lies in its parallel processing capability and pipeline operation mode, which should be much faster than software in principle.

It's like using many CPUs to process data at the same time, and eliminating a lot of useless operations, such as retrieving data.

4.The main reason for the view that "the performance of processing such as IP fragment reassembly, decompression, and packet correction is very low" is mainly because the design of FPGA for data processing is more difficult than that of software. It's like using CPP to write and decompress and using machine code to design decompression, the latter is obviously much more difficult, and it has a lot to do with the level of the designer.

At the same time, how to design the memory interface is also critical.

5.The concept of the so-called assembly line, you can imagine the automobile production line. There are many stations on the production line, and related processing and production are carried out at the same time, and the raw materials enter from the production line, and the corresponding processing process is completed step by step through the assembly line.

The advantage of a pipeline is that the data throughput is large, but the disadvantage is that the data processing time is long. Just like the automobile production line, a car can leave the factory in one minute, but the process from raw materials to the car is far more than 1 minute.

FPGAs are just a development tool. If you use FPGA to construct a simple system and attach software, the main performance is limited to the embedded CPU; If you construct a dedicated processing unit for a complex packet, the performance is still very high, but in general, the FPGA clock speed is low (no more than 100MHz), so the actual performance is not too high.

This, if you use the circuit to deal with this, of course it is difficult, the FPGA is the hardware, the ones you said should be handled by software, it is the protocol layer and the application layer, the FPGA generally does the firmware, in the physical layer.

Under normal circumstances, the conf done of the FPGA chip will not be shorted to ground when the power is not on.

If the program can be burned to indicate that the jtag is no problem, the program does not run because after the flashing is completed, the chip also has to detect the signal of conf done, if it detects that conf done is low (at this time, it is usually the case that the external pull-up is a problem or it is a situation that compares the groove cake - the chip has a problem with the pin), it is considered that the configuration has not been completed, so it will not run the program.

You will also need to provide some information.

After the program is flashed, check whether the nconfig and nstatus signals are high or low.

Let's do the test first:

1. Test whether there is a short circuit between the power supply and the ground.

2. Does conf done have a 10k pull-up resistor? Try a different resistor.

3. Finally, try to add a PF capacitor to ground in conf done to see if you can run.

I don't know who you're going to compare to. I guess it's compared to traditional ASICs.

1.Cost. In the low-end field, FPGAs have the advantage of replacing ASICs, but it is more difficult in the high-end, because the cost of high-end FPGAs is very high, unless the volume is not high, ASICs are definitely much more cost-effective;

2.Power consumption. This is also evident in the high-end segment. Achieving the same logic and speed, using FPGAs consumes much more power than ASICs.

3.Velocity. Even high-end FPGAs have lower rates than ASICs, and the main bottleneck is at the switching point of their programmable cabling resources.

The downside is that it's expensive.

And the advantage of data processing is that it is difficult to deal with some complex control logic, although there are state machines, but there is still a gap.