Does the CPU ignore all interrupt requests when the IF 0 flag is signed?

When the port is open, it will return UDP packets, and when it is not open, it may return ICMP messages, I thought that the port would definitely return ICMP messages if it is not open, but after being instructed by others, and then capturing and testing, it is not necessarily necessary to return ICMP messages.

The intr is a shieldable interrupt request signal, which is active at a high level and is triggered by a level. 8086 The 8088 CPU responds to the request for INTR, depending on the state in which the interrupt is allowed to trigger the flag if. If if=1, the company responds to the request of INTR, pauses the execution of the current subsequent instructions, and switches to the execution of the interrupt service program. If if=0, the request for intr will not be answered.

The interrupt allows the trigger flag if to be set to 1 by the STI directive and cleared by the CLI directive. Therefore, the response to the INTR interrupt can be controlled with software. When the system is reset or when the 8086 or 8088 CPU responds to the interrupt request and sets if=0, to allow the INTR request, you must first use the STI command to make if=1 before responding to the INTR request.

The CPU response masked the process of interrupts:

The CPU receives an interrupt request signal on the intr pin, and if if=1 at this time, and the current interrupt has the highest priority, the CPU will start responding to the external interrupt request after the current command is executed. This is to say that the CPU sends two negative pulses through the INTA pin in a row, and the peripheral interface sends an interrupt type code on the data line after receiving the second negative pulse

1. Put the interrupt type code into the scratchpad and save it;

2. Put the contents of the flag register into the stack to protect the interrupt state;

3. Clear if and TF to zero;

4 Protect breakpoints. IP and CS content into the stack;

5. According to the current interrupt type code, find the first address of the corresponding interrupt subroutine in the interrupt vector table, and load it into IP and CS, so that it can be automatically directed to the interrupt service subroutine for execution.

Answer: aintr: can mask interrupts, affected by the flag bit if, allow when if=0, reject when if=1.

NMI: unshielded interrupt, not affected by flag bit IF.

First of all, be clear about what is"Interrupts can be masked".

A maskable interrupt is an external interrupt, which is an interrupt that the CPU can not respond to. That is, when such an outage occurs, the CPU can ignore it and continue to do what it is doing;

However, whether the CPU responds to maskable interrupts depends on the setting of the if bit of the flag register. When the CPU detects a maskable interrupt message, if IF=1, the CPU must respond; If if=0, the CPU ignores it, which is equivalent to being blocked.

When the CPU responds to an interrupt, it enters the interrupt cycle. During the interrupt cycle, the CPU automatically completes a series of operations, such as:

1) Protect program breakpoints. Protecting a program breakpoint is to save the contents of the current program counter PC (program breakpoint) to memory. It can exist in a specific cell of memory, such as address 0, or it can be stored in a stack.

2) Look for the entry address of the interrupted service program. Since the end of the interrupt period enters the referencing period of the next instruction (i.e., the first instruction of the interrupted service program), it is necessary to try to find the entry address of the interrupted service program during the interrupt period. Since there are two ways to get an ingress address, there are also two ways to find an ingress address during an outage cycle:

Second, during the interrupt period, the first address of the program (also known as the interrupt identification program) of the software query entry address is sent to the PC, so that the CPU executes the interrupt identification program and finds the entry address (corresponding to the software query method).

3) Off the outage. In order to ensure that a series of operations required by the CPU after the response will not be interfered with by new interrupt requests, the interrupt must be automatically turned off during the interrupt cycle to prevent the CPU from responding to new interrupt requests. Standard R-S triggers are available for the Interrupt Trigger EINT and Interrupt Flag Trigger INTs.

When the interrupt period is entered, t is"1"state, the original output of the trigger has a positive jump, and after inverting, a negative jump is generated, so that the EINT is set to 0, that is, the shutdown is interrupted.

The above-mentioned operations such as protecting breakpoints, finding ingress addresses, and turning off interrupts are all performed by an interrupt implicit command during the interrupt cycle. The so-called interrupt implicit instruction is an instruction that is not available in the machine instruction system, and it is an instruction that is automatically completed by the hardware during the interrupt cycle of the CPU.

The interface address of external interrupt 0 is 0003h, is the a wrong knock here, hehe the interface address of external interrupt 1 is 0013h

Internal interrupts T0 and T1 are 000bh and 001bh respectively, and the serial interrupt address is 0023h

The answer is a, the answer to this a is not a mistake, it should be 0003h

The request signal that appears on the INTR line is level-triggered, and its sudden appearance is asynchronous, and the hall judgment is synchronously changed by the rising edge of the CLK inside the CPU. The interrupt request signal on the intr line must be maintained until the end of the current instruction. If if=1, the CPU responds to interrupt requests, and the CPU responds at this time.

If CPU=0, the CPU is considered to be in the interrupted state. If bit, you can use the command STI to set it, that is, open the interrupt.