What signals did the 8086 CPU send out in a minimum mode bus write cycle, and what was the use of ea

T1 Status: IO M indicates whether the CPU is reading data from memory (1) or from IO port (0). The CPU then issues a 20-bit address to read memory from the address state multiplex line (A19 S6 A16 S3) and address data multiplex line (AD15 AD0), and a 16-bit address from AD15 AD0 when accessing the IO port.

In order to latch the address, the CPU outputs a positive pulse from the ALE pin in the T1 state as an address latch signal. If you need to read data on a high 8-bit data line (odd address reads one word), bhe= 0. In order to control the bus transceiver 8286 data transmission direction, r dt = 0.

T2 state: The read signal RD starts to go low (active), den=0, which is used to open the bus transceiver 8286. T3 Status:

The CPU detects the Ready pin signal. If ready is high (active), it means that the memory or IO port is ready for data and enters the T4 state. If Ready is low (invalid), it means that the memory or IO port is not ready for data, and one or more TW states are inserted until Ready becomes high.

T4 state: At the falling edge at the junction of T3 (TW) and T4, the CPU samples the data on the data bus and reads the data.

The 8086 can work in two working modes, namely minimum mode and maximum mode.

One: Minimum mode and maximum mode.

1: Minimum mode: That is, there is only one microprocessor in the system, 8086 (or 8088).

The minimum mode is a single-processor system. All control signals required in the system are provided directly by the 8086 (or 8088) CPU itself.

2: There are two or more microprocessors in the maximum mode system, that is, in addition to the main processor 8086 (or 8088), there are also coprocessors (8087 arithmetic coprocessors or 8089 input and output coprocessors) file rent. The maximum mode can form a multiprocessor system, and the required control signals in the system are provided by the bus controller 8288.

Two: Differences. 1：

The maximum mode is relative to the smallest mode. Maximum mode is used in medium or large 8086 8088 systems. In a maximum-mode system, there are always two or more microprocessors, one of which is the 8086 or 8088, and the other processors are called coprocessors, which are used to assist the main processor.

2: There are two coprocessors with 8086 8088, one is the numerical operation coprocessor 8087, and the other is the input and output coprocessor 8089.

3:8087 is a processor dedicated to numerical operations, which can implement many types of numerical operations, such as high-precision integer and floating-point arithmetic, and can also perform transcendental functions.

Such as trigonometric functions.

logarithmic function).

The choice of CPU working mode is determined by the hardware, if the 8086 8088 pin 33 is grounded, it will work in the maximum mode, and pin 33 will be connected to the high level.

then works in the minimum mode. The 8086 8088 CPU has 8 pins (No. 24 and No. 31) with different functions in two different modes of operation.

The main features and differences of the 8086 CPU when working in minimum and maximum mode are as follows:

Minimum mode:Only an 8086 CPU and up to 64KB of memory are required to work.

No external devices are required, and all control signals are generated by the CPU.

There are only 20 address buses, so the maximum addressing capacity of 1MB is suitable for simple single-processor systems.

Max Mode:Up to three coprocessors and seven external devices can be connected.

24 address buses can be used, so the maximum addressing capacity is 16MBCPU and the coprocessor is communicated using a dedicated bus, improving the operational efficiency of the system.

Suitable for complex multi-processor systems.

For example, if we need to build a simple single-processor system, we can simply use the minimum mode for lifting. If we need to build a complex multiprocessor system, we need to use maximum mode and connect multiple coprocessors and external devices. At the same time, the maximum mode can improve the operating efficiency of the system, so it is also more suitable for use in some fields with high performance requirements.

The basic bus cycle is 4 clock cycles, and the interval between each clock cycle is called a t-state;

3.Write bus cycle: A D bus forms data to be written and remains until the end of the bus cycle (T4), while T3, T4: For read or write bus cycles, AD bus is data;

4.The time that a cycle signal of the main clock of the system lasts is called the clock cycle (t); The process in which a microprocessor performs a read/write operation through an external bus pair and a memory or IO port call cover is called a bus cycle; The time it takes for a microprocessor to execute an instruction (including the total time required to retrieve and execute an instruction) is called the instruction cycle; Relationship: A bus cycle consists of several clock cycles; An instruction cycle consists of several bus cycles.

When hold is valid and a response is received, the external processor transmits data over the bus, hold 1, which indicates that the outside party requests to relinquish the bus.

All wires with "three states" are placed in a high-impedance state, such as S2S1S0Rq GT0, RQ GT1, Lock, Nu MX, etc.

The Intel 8086 has four 16-bit general-purpose registers, which can also be accessed as eight 8-bit registers, and four 16-bit index registers (including stack indicators).

Data registers are often used implicitly by instructions and require complex register configuration for scratch values. It provides 64k 8-bit output input (or 32k 16-bit), as well as fixed vector interrupts. Most instructions can only access one memory address, so one of the operands must be a register.

The base bus cycle of the 8086 is 4 clock cycles.

Each clock cycle interval is referred to as a t-state.

t2 Status:

Read Bus Cycle: A D bus prepares to receive data. Change the direction of the line.

Write Bus Cycle: Data to be written is formed on the A D bus and is maintained until the end of the bus cycle (T4).

T3, T4: For either read or write bus cycles, all data is on the AD bus.

TW: When the RAM or IO interface is not fast enough, a waiting state TW can be inserted between T3 and T4.

ti : When the BIU does not have a task to access operands and take instructions, the 8086 does not perform bus operations, and the bus cycle is in the idle state ti.