What tools to use to design based on the Verilog language

Learn the verilog language dry annihilation method.

Module Definition, Interface Definition, Module Instantiation, Register Definition, Line Definition, Always Block.

The biggest difference between Verilog and software languages is that it describes circuits and writes them in a fixed way. Starting from the basics, it's important to accumulate small circuit description methods like timers and decoders!

Verilog encourages innovation in circuits, not in describing methods.

Learn FPGA's important concept of Cha Erection: the right design! = correct rtl, but "right design == right rtl + right timing constraints".

Proper timing constraints typically include:Pin constraintswithClock constraints

Verilog Abstraction Level:Behavioral levelRTL levelGate levelSwitching stage

Behavior level: Modules on behaviors and technical indicators.

RTL level: A module that describes the logical execution steps.

Gate: A module in which logical components are connected to each other.

Switch Stage: A module for physical properties and layout parameters.

Logical function definitions: assign declarations, instance components, and always blocks.

The assign statement is one of the most commonly used ways to describe combinatorial logic.

Always blocks can describe both combinatorial and sequential logic.

Always is not next to a cluster of loops, always is a process block. always@ (a or b or c) We can often see the always statement such as the above sentence, when the a, b or c signal in parentheses changes, the always module is activated, and the statement in the module can be executed. The signals in parentheses are called the list of sensitive signals.

All the always-blocks have a parallel relationship with each other, and who is first and who is last does not affect the order of execution.

for is a circular statement, but it cannot be synthesized (compiled). for is usually used in test files. Or it can be used to attach an initial value to the RAM. For example, a RAM space is defined.

reg [n-1:0] mem [word-1:0];

You can use a for loop when initializing the early oak.

integer i;

for(i=0;In this way, all the contents of RAM are defined as 0. However, for cannot be used in circuit entities.

Verilog is a hardware description language, used to describe the structure and behavior of hardware, not software, not C, very different, there is no such thing as loops. It can be said that the program made by verilog is actually the same thing as the drawing of hardware engineers, each statement, each module, represents the use of a chip, and then connected to the line so that the hardware circuit comes from the loop, pay attention to the good difference.