How to set up the 8259 in protected mode

The 8259 can prioritize IR7 IR0 requests in one of four ways.

Full nesting mode (default arrangement, AT uses this mode), special full nesting mode, priority automatic loop mode, and priority special loop mode.

1) Fully nested.

Interrupt requests are handled with priority 0 7, and requests on IR0 are 0 with the highest priority; Requests on IR7 are level 7 with the lowest priority.

If there is a request on IR7 IR0, the PR compares the request to the priority in the ISR and only if the priority of the request is greater than the priority in the ISR, the 8259 makes a request to the CPU.

2) Special full nesting method (specified by ICW4).

In the same fully nested mode, it is processed according to 0 and 7 levels, and the 0 level has the highest priority.

When the priority of the request that appears on the IR line is greater than or equal to the priority in the ISR, 8259 makes a request to the CPU. This prioritization is used for the main 8259 of a multi-slice 8259 cascade system. The input IR of the primary 8259 is a request int from the 8259, which has a different priority for different IR lines from the 8259, but is all the same level in the primary 8259.

Therefore, when the CPU is processing a request from 8259, if there is a request from the same higher priority from 8259, the primary 8259 should be allowed to make a request to the CPU.

3) Priority automatic cycle mode (specified by OCW2).

In this prioritization arrangement, the priority queue is varied, and when an interrupted request is processed, its priority is automatically lowered to the minimum.

Initially, the priority queue is: IR0 (highest) ......IR7 (minimum).

If IR0 has a request, after IR0 is processed, the priority queue is: IR1 (highest)....-ir7…--ir0 (minimum).

If there is another IR4 request, after the IR4 request is processed, the priority queue is: IR5 (highest)....-ir7…--ir0…--IR4 (minimum).

4) Priority special round-robin mode (specified by OCW2).

Similar to the automatic cycle of priorities, but initially the highest priority is specified programmatically.

Priority Real-time: Occupies all available resources, and when the available resources are insufficient, the resources occupied by high, higher (higher than the standard), average, lower, and free-level programs are preferentially used.

High: Occupies available resources, and when the available resources are insufficient, it occupies higher and generally lower free resources, and will give way to real-time programs.

Higher: ......Ibid., omitted not to fight), occupy the general lower free resource ,......General: ......The resource ,...... occupied by programs that occupy lower levels of freedomLower:

Occupy the ,...... of resources occupied by the free level programFreedom: You can freely obtain the resources occupied by other programs only when all the resources are sufficient, otherwise the resources occupied by yourself will be ceded to other programs.

I suggest you go to ** and see what is available.

The cascade in the microcomputer principle refers to:

Interrupt handling is a task that the operating system must complete at IBM

In the PC, an interrupt control chip (PIC) - 8259A is commonly used to assist the CPU to complete interrupt management. In real mode, the initialization of the Interrupt Control Chip (PIC) 8259A is done automatically by the BIOS, but in protected mode, you need to program the initialization yourself. This paper describes in detail the exploration in this direction from the perspective of operating system writing, and finally verifies it through experiments with pyos.

Cascade is generally applied in the microcomputer principle in interrupt processing (8259 chip processing), generally an 8259 chip can only accept requests from 8 external interrupt sources, and then manage these requests, sort and optimize them, and then send them to the CPU for request interruption.

But when there are more than 8 external interrupt request sources, it is necessary to use multiple 8259 chips to process, and these 8259 chips have to send the interrupt source they manage to the CPU for request, but the CPU only has an intr pin to accept external interrupt requests, that is, only one 8259 chip is allowed to be connected to the CPU, so what about the other 8259 chips, aren't the requests they manage unable to be submitted? At this time, we deal with the request submission end of the other 8259 chip (the chip that is not directly connected to the CPU --- from the 8259 chip) to the interrupt requester of the 8259 chip (the main 8259 chip) that has been connected to the intr pin of the CPU, as an external request source.

In essence, those requests from the 8259 chip to the interrupt source managed by themselves are submitted to the main 8259 chip, and the main 8259 chip is required to be transferred to the CPU for processing, which is called the cascade of interrupt processing.

Because the CPU will be before each trigger use"Contact:"on the protection mode for maximum efficiency.

Are you just starting to learn Linux?

First of all, you need to understand that Linux is an operating system with a protected mode (which is what you wrote above: fully run the fish protected mode). Send me a message for more details.

But you'll have to give it to me first, haha). Linux, on the other hand, is known for its efficiency and flexibility (colloquially speaking, the ability to multi-task, multi-user).

The relationship between the two:

Because the Linux system divides memory into kernel area and user area.

The kernel area houses and runs the core**, and of course, the user area also houses and runs user programs.

Because of its kernel relationship, this system can fully call the performance of the CPU. So it's not your own understanding that you can't "make full use of CPU performance" if you don't "run fully in protected mode"?

Because the system itself is running in protected mode.

I don't know if you can understand it. I'm sorry to tell you, uh...

ps Damn, I really despise the people who copied above. Playing for so long is not as fast as he copied. Depressed.

Because the real mode is prepared for the early 8088 type of CPU, the address line is only 20 lines, that is, the read and write of the memory address is within 1M. Protected mode is the only way to make the most of today's huge memory.

1The D3 bit of all ICW1 is used to set the interrupt trigger mode.

d3 = 1, level trigger mode; d3 = 0, edge triggering mode, for example, initialization command word 00011011b = 1bh, meaning:

D7 D5=000, which is the default value of 8086 8088 CPUs D4=1, is the ICW1 initialization flag.

d3=1, set the interrupt to the level trigger mode.

D1=1, monolithic 8259, no need to write ICW3

d0=1, write icw4

Example of the 8259a initializer:

mov al， 1bh ;;icw1 initialization command word to alout b0h,al ;; The initialization command word saved in al is written to icw1mov al, 42h ;; icw2 initialization command word to alout b1h, al ;; The initialization command word saved in al is written to icw2mov al, 03h ;; icw4 initialization command word to alout b1h, al ;; The initialization command word saved in al is written to ICW4

Because 8259a has only one address line, the primary square of 2, which is the two port addresses.

The 8259A has only two port addresses.

The main features of the 8259A are as follows:

The 8259A is a programmable interrupt priority management device, and the meaning of "programmable" is that its working state and operation mode can be set by software to meet the needs of different application environments. Its main features are:

1) It has eight levels of priority control, which can be extended to 64 levels of priority management through multiple 8259a cascades;

2) Separate shielding can be achieved for any level;

3) Provide programmable flag code for the CPU, and interrupt type code for the 8086 CPU;

4) It has a variety of priority management models, and most of these management models can change dynamically.