The instruction that controls the CPU internal interrupt allow trigger is

Answer]: The trigger of the call for interrupted request in B is the IRR in 8259; The interrupt shielding trigger is IMR inside the Hop Chun 8259; Located inside the CPU is the Age Let Interrupt Allow Trigger IF.

Summary. The operation that allows the interrupt trigger to be set to 0 is done by the interrupt controller. An interrupt controller is a special peripheral that controls the occurrence and handling of interrupts, and can set interrupt triggers to 0.

When an interrupt occurs, the interrupt controller detects the interrupt request and sets the interrupt trigger to 0 to prevent the interrupt from reoccurring. The interrupt controller then passes the interrupt request to the CPU so that the CPU can handle the interrupt. Finally, the CPU executes an interrupt handler to handle the interrupt request.

The operation that allows the interrupt trigger to be set to 0 is done by the interrupt controller. An interrupt controller is a special peripheral that controls the occurrence and handling of interrupts, and can provision interrupt triggers to 0. When an interrupt occurs, the interrupt controller detects the interrupt request and sets the interrupt trigger to 0 to prevent the interrupt from relapsing for the rest of its life.

The interrupt controller then rolls and the interrupt controller passes the interrupt request to the CPU so that the CPU can handle the interrupt. Finally, the CPU executes an interrupt handler to handle the interrupt request.

I'm sorry I don't understand, but can you elaborate on that?

The operation that allows the interrupt to be set to 0 is done by the interrupt controller. An interrupt controller is a special peripheral that controls and sends interrupt requests to the processor. It can also control the interrupt response of the processor and send the interrupt response to the peripherals.

The interrupt controller controls the interrupt priority of the processor and sends the interrupt priority to the processor. In addition, it can control the interrupt masking of the processor and send the interrupt masking to the processor. The interrupt controller controls the processor's interrupt trigger and sets the interrupt trigger to 0.

When the processor receives an interrupt request, the interrupt controller sets the interrupt trigger to 1 so that the processor can receive the interrupt request. When the processor finishes processing the interrupt request, the interrupt controller sets the interrupt trigger to 0 so that the processor can continue to execute normal instructions. The function of the interrupt controller is not only to set the interrupt trigger to 0, but also to control the interrupt priority of the processor and send the interrupt priority to the processor.

It can also control the interrupt masking of the processor and send the interrupt masking to the processor. In addition, it can control the interrupt response of the processor and send the interrupt response to the peripherals.

Answer]: bThis question tests the basic knowledge of computer hardware composition. The CPU is the control center of a computer, which is mainly composed of components such as combinators, controllers, register banks, and internal buses.

The controller is composed of a program counter, an instruction register, an instruction decoder, a timing generator, and an operation controller, and it is the "decision-making body" that issues commands, that is, completes the coordination and directs the operation of the entire computer system. Its main functions are: taking an instruction from memory and pointing out the location of the next instruction in memory; The instructions are decoded or tested, and the corresponding operation control signals are generated in order to start the specified actions of the file limbs; Command and control the flow of data between the CPU, memory, and I/O devices.

The program counter (PC) is a special register, with two functions of register information and counting, also known as the instruction counter, before the program starts to execute, the starting address of the program is sent to the PC, which is determined when the program is loaded into memory, so the initial content of the PC is the address of the first instruction of the program. When an instruction is executed, the CPU will automatically modify the contents of the PC so that it always maintains the address of the next instruction that will be executed. Since most instructions are executed sequentially, the process of modification is usually as simple as adding 1 to the PC.

When a transfer instruction is encountered, the address of the successor instruction is obtained from the address of the current instruction plus a displacement of forward or backward transfer, or from the address of the direct transfer given by the transfer instruction.

In the operating system, when an interrupt (or event) occurs, the CPU reacts with ().

Continue to execute the current program and hand over the outage event to an external device for handling.

Continue to execute the current process and wait until the program is over to deal with the outage.

If you continue to execute the current program, you can ignore the occurrence of the interruption event.

Suspend the program that is being executed, and automatically turn the balance to clear the correct search to deal with the interruption event.

Correct answer: d

The CPU is set up to run the controller by starting the command, and while the controller is running, the CPU can run another process.

1.A process is a one-time running activity of a program and is a dynamic concept. A program is an ordered set of static instructions, a static concept.

However, the process manuscript is not disturbed and left the programA process can execute one or more programs. For example:

When a process compiles the key C source program, it has to perform several programs such as pre-processing, lexical analysis, generation and optimization.

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The ** that causes the interrupt event and makes the interrupt request is called (); The address of the next instruction that the interrupted CPU is executing is called (). Refers to the address of the memory of the Kaila, where the first instruction of the service program is interrupted.

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Dear, I've been waiting for a long time. We're happy to answer for you! The ** that causes the mid-sale minqin break event and the request for the mid-sale promotion break is called (interrupt source); The address of the next instruction that the interrupted CPU is executing is called (breakpoint).

Interrupt source ) refers to the address of the memory cell where the first instruction of the interrupt service program is lost.

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The 8259A assists the CPU with interrupt handling, through which the following can be done:

1] Priority queuing management.

Assign the interrupt level of the interrupt source based on the priority of the task or the special requirements of the device. The 8259a is fully nested. Priority queuing management in multiple ways, such as circular priority and specific shielding.

2] Interrupt intr can be masked

When there is a "high" valid signal from an external source on the CPU's INTR pin, a hardware shieldable interrupt request INTR is generated, which can be disabled by the CPU with the CLI command or allowed by the STI. Only when the intr is allowed, the CPU sends the interrupt response signal INTA, and the interrupt source must provide the interrupt type number to the CPU in order to find the interrupt service entry. Interrupts with interrupt numbers 08 0fh and 070h 077h in the interrupt vector table belong to this type of interrupt (see table).

It is clear that this interruption is generated by an external device.

3] Provide the interrupt type number.

The most prominent feature of 8259A is that it has the ability to address the entrance address of the interrupt service program, that is, when the CPU responds to the interrupt request, the population address of the interrupt service program can be found through the interrupt type number provided by 8259A, and it can be transferred to the interrupt service program for execution. 

4] Shielding and opening of interrupt requests.

The 8259A has the ability to shield or open external devices that make an outage request. It can be seen that the use of 8259A allows the system to manage hard interrupts without additional circuitry, and only needs to program the 8259A to manage 8, 15 or more hard interrupts, and also implement vector interrupts and query interrupts. 

The 8259A can determine the interrupt priority, provide the interrupt type number, shield the interrupt input and other functions, and provide the interrupt service program entry address for the CPU during the interrupt response cycle.

During the interrupt response cycle, the 8259A provides an interrupt type code for the CPU to respond.