Verilog language, confusion about state machines

In the state machine time series, the assignment is generally "<="."It's a lot, if you don't have a special need, don't use "=".

4'd0:begin if(idle_count[5:0] == 6'd50) flag = 1;

else idle_count[5:0] = idle_count[5:0] +6'd1;

state[3:0] = 4'd1; end

4'd1: begin if(falg = 1) falg = 0;……state[3:0] = 4'd2; end

4'd2: begin ……state[3:0] = 4'd0; end

case statement'After d0 satisfies state[3:0] = 4'd1, this assignment is performed immediately, then 4'd1 is satisfied again, and then it goes all the way, although your flag is set to 1 at 50, but then it is set back to 0 below, so the timing can't be seen, will it be this problem, it is recommended to change the blocking assignment.

I don't know if I understand it right, let's take a look.

1 . idle_count[5:0] == 6'd50, the flag changes from 0 to 1, and does not enter state 1;

2 . idle_count[5:0] !

6'd50, the flag is still 0, there is no change, enter state 1, and then, judge if(falg ==1) and falg=0 cannot meet the condition, so it is stuck in this step;

3.From what you add below, the condition for state 0 to enter state 1 is rxdata!== 1；When rxdata == 1, the flag will change from 0 to 1;

The initial value of your idle count is 000000, and the initial value of your state is also 0000

So your state machine is stuck in the first step.

4'd0:begin if(idle_count[5:0] == 6'd50) flag = 1;

You need to add a state change to this if, otherwise the state will not maneuver.

From 4'd0 jumps to 4'd1 has idle count[5:0] = 6'd0;5:0] = 6'd0;This sentence is back to 0, and if the flag changes, the idle count can reach 6'd50, if the content in your ellipsis is irrelevant, then the idle count will not change, and the flag will not change.

Don't use = for timing logic, use <= should be fine.

A finite state machine is a sequential logic circuit whose output depends on the past input portion and the current input portion. A finite state machine can also be thought of as a combination of combinatorial logic and register logic. State machines are particularly suitable for describing things that happen in a sequential or logical manner, which is actually the nature of state machines.

A state machine is a way to describe events that have a logical sequence or sequence of time.

In practical applications, state machines can be divided into two categories according to whether the output of the state machine is related to the input conditions, namely Moore state machines and Mealy state machines.

parameter s_idle = 0;

parameter s_1 = 1;

parameter s_2 = 2;

reg [2:0] r_state = 0;

reg [2:0] r_next_state = 0;

State machine initialization, note that <=

always @ posedge i_clk )begin

r_state <= r_next_state;

end state transfer, pay attention to the sensitive list, pay attention to use =

always @ i_en or r_cnt1 or r_cnt2 )

begincase ( r_state ):

s_ilde;

if ( i_en )

beginr_next_state = s_1;

endelse

beginr_next_state = s_idle;

ends_1:

if ( r_cnt1 = 100 )

beginr_next_state = s_2;

endelse

beginr_next_state = s_1;

ends_2:

if ( r_cnt2= 100 )

beginr_next_state = s_idle;

endelse

beginr_next_state = s_2;

endend

Finally, assign values to your variables based on different states.