How to connect a high speed serial ADC to an FPGA?

Hehe. I don't know what FPGA you're using. The data clock rate is quite high. I deliberately took a look at the information of this 9222. I think this design is difficult on the IO side.

Answer: The wiring of the differential signal of LVDS in the PCB not only needs to be of equal length, but also the impedance is required. The documentation for Altera and Xilinx has such example designs

Second, it is the direct connection between the ADC and the FPGA: the Altera series supports devices that support 600Mbps

Cycloneiii, Stratixii and above, as well as the latest ARRAIA, can support up to LVDS 600+. Xilinx side Spartan3, Vertix series support.

Third: FPGA. Differential pairs are constrained before they can be used.

Whether it's Xilinx or Altera. The first is the pins. You can constrain to the corresponding pin from the assignment or ucf.

The corresponding legend in the Pin Planner will show that the input ports of a pair of differential signals are represented by P and N respectively. The second is the need to constrain the delay time from the input to the first register. See the example below.

The data window may indeed be a bit small. Hehe, this AD seems to be used for medical purposes, and the accuracy is very high.

Give us a reference design.

altera：

The first FAQ talks about the megafunction of the high-speed interface in Quartus. You can take a look when you are free. It is helpful to understand the full range of IO standards.

The second FAQ is the example and stratix series. There are two PDFs. Internally included: PCB wiring requirements. and the use of internal ports.

Xilinx:

The first one is the PCB requirement:

But xilinx's example design... I searched for a long time, only conclusive... Constraints and reference designs are too scattered... So I searched and searched but didn't find it.

If only Xilinx were used. If not, look for your local FAE. Hehe, I really can't help it.

Hello, I'm also doing the project of high-speed serial AD connection to FPGA, I don't know, can you refer to your FPGA about the collection of AD**.

It has been sent to your mailbox, please check.

What kind of design do you want to achieve?

Sensible Electronic Design VGZ

Achievable;

An FPGA development board with a serial port, a serial cable, and a computer with a serial port are required.

Achievable;

Series FPGA development board, serial cable and a PC with a serial port.

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image]20 How to connect an ADC to an FPGA board.

Nowadays, some FPGAs have integrated ADC modules inside, which can implement the functions of ADCs. If it is an ordinary FPGA chip with a pure logic array, it is generally connected to an external ADC chip to realize the AD sampling function. However, if the performance requirements of AD sampling are not high, you can also use the RC circuit and the LVDS interface of the FPGA to implement a simple AD sampling.

Absolutely, but FPGAs can only implement the digital part.

When sending, it is simple, as long as the working clock is divided to the baud rate, the output data can be strung and skeweed; When receiving, the trouble point needs to detect the start bit, and then receive the data bit and the stop bit, and the working clock needs to be divided to n times the baud rate, so that each received symbol can be sampled n times, and a judgment is made in these n times, so that it can prevent interference.

You have multiple links in this matter, you have to analyze them separately, AD sampling, RAM storage, DA output, it seems that the latter is OK? You can check the DA and RAM, and you can save the sinusoidal data or the sawtooth waveform data to see the waveform confirmation. If the problem is confirmed to be AD, there is only one, the bandwidth of AD is not enough, or the sampling frequency is not enough.

FPGA can't do it on its own, and you can realize your requirements through a microcontroller.

1. The FPGA board on the hardware must have an RS232 interface to connect with the PC.

2. Write a serial port receiving module on the software, and set the baud rate and data bit width.

That's all there is to it.

I have a verified serial verilog program, which can be used directly.

Before it is sorted out, the data sent by the computer to the FPGA is put into a register, and then the data in the register is used as the crossover coefficient. It's happening.