Why does T1 saturate when the TTL inverting circuit input is low?

The T1 input is low, the T1 emitter is positively biased, the base potential is limited, and the collector is back-biased.

At this time, the T2 collector junction is reversed, and the emission junction is not able to reach the conduction condition because the base potential is too low, so T2 is cut-off. R2 provides bias to the T3 base, T3 is on, and the output is high.

T1 input is high, T1 is cut-off, due to the base potential of T1 is 5V, the BC diode is forward conducted, T2 is turned on due to bias, T4 is also turned on, and the output is low.

If T2 is a triode with a common emitter, it is designed to ensure that when the circuit input is high, T2 will obtain a larger base current, so that T2 will be turned on and enter a shallow saturation state, and the output of T2 will be low after saturation conduction, so that the inverting effect will be realized.

The voltage between the two red dots will not be equal, are you mistaken?

It should be that the base voltage is higher than the collector voltage, that is to say, the triode at this time only works as a forward diode; T2 works due to the base current, and makes T5 saturated and conducted, and the output is low, which realizes the function of inverter;

When the input of A is low, T1 works according to the transistor mode and enters the saturation region, and the collector voltage is close to the A level, causing T2T5 to cut off T4 and turn on, and the output is high;

When vi=vih, the voltage between the two red dots should not be equal, because when the input is high, the T1 tube works in the reverse amplification region, and the emitter potential of T1 is 2V. The resistance between the triode b-c is very large, and it can generally be treated as infinity.

The landlord asked about the TTL inverter, but the upstairs said the conclusion of the CMOS door. TTL doors and CMOS doors are not the same!

It's not the same for CMOS NAND gates. Since there is no current flowing out of the gate, there can be no voltage drop across the resistor, so no matter how big the resistor is, the input is low and the output is always high.

In the case of TTL NAND gates, because their structure is different from that of CMOS NAND gates, the size of the ground resistance connected to the input directly affects its output.

1 When the resistor connected to the input is large (e.g., 20K here), the current flowing out of the NOT gate creates a voltage drop across the resistor, and the input appears high, and the output output is low.

2. When the resistance of the input terminal is relatively small (such as several hundred ohms), the voltage drop formed by the current flowing out of the non-gate is less than 1 4V, so the input terminal is low, and the output terminal is high.

Hope this helps you a little!

The inverter input ground is the same as the series resistor after grounding, and the output is high.

Whether it is directly grounded or resistor-grounded, it will output a high level.

I happened to see here, T2 conducts to make CE on, and the current flows through the base of T2 to the emitter, forming a loop, so VC2 is originally equal to the voltage at the upper end of R2, that is, VCC, but after the path, the voltage is divided below, so that the VC2 voltage decreases, and the VE2 voltage can make T5 on, but why is T4 cut off???

The emitter and collector of T1 are reversed, which is easy to understand and does not need to be explained.

How the TTL inverter works.

When input vi = high).

VB1= is sufficient for T1 (BC junction), T2 (BE junction), and T3 (BE junction) to be turned on at the same time, once VB1 = fixed value), then the V1 emission junction must be cut off (inverted amplification state).

VC2=VCES+VBE2= is not enough for T3 and D to be turned on at the same time, and both T4 and D are cut-off.

v0= (low).

When input vi = low).

VB1 = not enough to make T1 (BC junction) T2 (BE junction) T3 (BE junction) turn on at the same time, T2 and T3 are all cut off, and at the same time, VCC---RC2---T4---D --- load forms a path, T4 and D are both on.

v0=vcc-vrc2 (omitted)-vbe4-vd= = high level) Conclusion: high input, low output; Low input, high output (non-logical).

1;When the input VIN is high (1), T3 is cut-off, T2 and T4 are on, and the output is low (0), and the collector current IC of T4 flows through the load current, which is what we usually call the load capacity.

2；When the input VIN is at the offset level (0), T2 and T4 are cut-off, T3 is on, and the output is high (1), and T4 has no collector current IC outflow. The T3 collector current flows to the load.

3；You have to take a hard look at how T2 is working to see why.

I've figured out the concept of implementing the "NOT gate" because the TTL inverter can implement it, but the netizens who asked me about the circuit need to note that this part of the circuit is extracted from the whole circuit, as long as a 5V

In the transistor amplification circuit, whether the transistor is saturated and conductive is related to the collector current and load resistance of the transistor. For example, if the common emitter basic circuit, RC is 1M ohm, under 5V power supply, as long as the IC reaches 5UA, the transistor will have already reached saturation.

For digital ICs, as you said, the VT2 reverse BC junction resistance is very large, for example, 100m, then the IC will be deeply saturated as long as it reaches it. This current is basically negligible for ICs that are calculated in several UA levels.

When the input is low, such as UI=UIL=, the emitter of VT1 is turned on, and the potential of the base potential of VT1 is clamped at 1V, then because the collector of VT1 has no other branch to provide current and voltage, VT1 is in a deep saturation state, and the collector voltage of VT1 is maintained, so that VT2 is in a cut-off state, so that the collector of VT2 is reversed, of course, the current leaking to the base is very small and negligible.

Transistor saturation means that the current provided by the collector is less than b times the base current, that is, the collector current is no longer proportional to the base current. In the circuit, the base current is 1mA, and the VT1 amplification factor is about 20, but the current supplied to the VT1 collector by the VT2 base is below, so VT1 is in deep saturation.

When the input is converted from high to low, the base charge of VT2 is quickly released by VT1, so that the working frequency of the circuit is increased and the main purpose of VT1 is used.

You post the circuit diagram first, otherwise how can others know how VT1 and VT2 are connected in the circuit?

Tell me the title of the book and I'll look it up.

When the input is high <>, T1 is in the diode state: the collector is forward conducted, and the emission amur source is reversed cutoff. God is like a god.