What is the output level when all the inputs of TTL and NAND gates are floating at the same time?

Something went wrong. The TTL input dangling has the same effect as if the input was high, and if the input was low, it would be meaningless whether the other inputs were low or high.

Because they are 1 for both non-outcomes. So when the input is high or dangling, NAND gates.

It makes sense. Note: CMOS AND NAND gates do not have a dangling state.

When the transistor. When the input terminal is suspended, there is no current from the base of the triode to the emitter, and the triode is cut off, and the output is low by amplifying the inverted phase, so the input terminal is suspended equivalent to the logic high level. In the actual circuit, the TTL and NAND gate inputs can be floated.

Suspended in the air, equivalent to infinity.

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Its logical relationship is "there is 0 out of 1, there is 1 out of 0", when all the suspension is both 0, the output is 1, high level.

An input port is left open and has no effect on the output of the circuit, while the TTL and NAND gates only have the characteristics of a logical relationship between the input and the NAND gate: the output is only present when all the inputs are at a high level.

If the extra input of the TTL and NAND gates can be connected to ground, the redundant inputs of the TTL and NAND gates can be connected to the high level VCC.

The power supply of TTL works at 5V, so the level of TTL is set according to the supply voltage of 5V. CMOS level, CMOS power supply working voltage is 3V - 18V, CMOS power supply working voltage range is wide, if your CMOS power supply working voltage is 12V, then the input and output level voltage of this CMOS should be suitable for 12V input and output requirements. That is, the level of CMOS, depending on what the working voltage of the power supply you use, 3V - 18V, all within the range of the power supply working voltage of CMOS, the specific value, depending on what the power supply working voltage you add to the CMOS chip.

TTL advantages:

The TTL level signal is ideal for the data transmission inside the equipment controlled by the computer processor, first of all, the data transmission inside the equipment controlled by the computer processor is not high for the power supply requirements and the heat loss is also low, in addition, the TTL level signal is directly connected with the integrated circuit without the need for expensive line drivers and receiver circuits; In addition, the data transmission inside the device controlled by the computer processor is carried out at high speeds, and the operation of the TTL interface meets this requirement.

In most cases, TTL communication uses parallel data transmission, which is not suitable for distances of more than 10 feet. This is due to both reliability and cost. This is because there are phase bias and asymmetry problems in parallel interfaces, which have an impact on reliability.

If there is an extra input terminal in the TTL NAND gate that can be grounded, it is connected to 0 after grounding, so that the input is 0 after the AND operation.

The redundant input terminals of TTL and NAND gates can be suspended, which is equivalent to connecting 1, but in the actual operation of the circuit, the circuit is not strong in anti-interference. Therefore, the TTL and NAND gate redundant inputs are generally connected to VCC.

If any input terminal of the NAND gate is low, the output of the other input terminals will always be high level no matter how the other input terminals change, so the input terminal of the NAND gate must be connected to the positive end of the power supply, otherwise the signal of the other input terminals will be blocked.

For TTL and NAND gates, the output is high as long as there is a low input at the input of the circuit, and the output is low only when all the inputs are high. According to its logic function, when an input terminal is externally connected to a high level, its logic function is not affected, according to this characteristic should be used the following four methods:

1. Connect the redundant input to a high level, that is, connect to the power supply through the current limiting resistor.

2. According to the input characteristics of the TTL gate circuit, when the external resistance is a large resistance, its input voltage is high. This leaves the redundant input empty, and the input is equivalent to an external high level.

3. Through the large resistance to the ground, which is also equivalent to the input terminal external high level.

4. When the working speed of the TTL gate circuit is not high, the signal source has strong driving ability, and the redundant input terminal can also be used in parallel with the input terminal used.

Software Engineering Concepts.

In software engineering, one of the principles of the overall structure design of the system: the fan-out coefficient of the module and the fan-in coefficient should be set reasonably.

Module's fan-in coefficient: The number of modules that are directly called when a module is called by other modules.

The fan-in, fan-out factor settings of the module:

The average fan-in, fan-out system of a good system is usually 3 or 4, and generally should not exceed 7. Menu call type module fan-in and fan-out system, common module fan-in system can be larger.

Modules that are too large: Cause the system to be broken down inadequately. Modules that are too small: Reducing the independence of the module and causing complexity of the system interface. Optimal module size: program coefficient is limited to 1 2 pages.

TTL should be connected to the NNOT gate redundant input to the high level, and TTL or NNOT gate redundant input should be connected to the low level.

1.The basic rs flip-flop consisting of TTL and NAND gates, when rd=sd=1, the flip-flop is in the original state.

2.The characteristic equation for the jk flip-flop is q*=jq'+k'q3.When TTL and NAND gate are no-load, the typical value of the output high-level UOH is about greater than When TTL and NAND gate are no-load, the typical value of the output low-level UOL is about less than the basic RS trigger composed of TTL and NAND gate, and when RD=SD=0, the trigger is indefinite.

For the redundant input terminals, they should be disposed of separately according to the function of the circuit: the redundant ends of the AND gate and the NAND gate should be connected to the high level, and the TTL gate circuit is suspended and equivalent to the high level. Whether the unwanted end is connected to the high level, the air or the low level, yes.

In a real circuit, the input pins of the NAND gate and the NAND gate should be connected high (i.e., the positive voltage connected to the power supply by resistor).

Go to the Digital Gate Circuits section. First, the two inputs of the TTL NAND gate are a triode with two transmitters, and the level of the levitation terminal A is clamped by the other input terminal B, because they have the same base C, and the voltage is B 0 7, A C 0 7 B; y＝（ab）＇＝bb）＇＝b＇＝（1b）＇＝b＇；Therefore, the chosen zero terminal is equivalent to being connected to a high level.

Generally speaking, we use tin to fix useless feet when making circuit boards, rather than attaching the feet to the circuit, that is, putting the feet in the air.

If the input terminal in the TTL integrated circuit is suspended (not connected to anything), it means that the input terminal is high (logic 1), but in practice, the input terminal that is not connected due to technology, pollution and other reasons is easy to touch other signal lines, resulting in input error signals, so it is recommended that the landlord connect the input terminal with high level or ground according to the circuit requirements when designing the circuit.

When any input (or multi) of the NOR gate is high (logic "1"), the output is low (logic "0"); The output is high (logic "1") only when all inputs are low (logic "0"), and in order for the idle end not to affect the circuit, it must always be low, so the idle side should be grounded.

In the actual circuit, the input pins of the NAND gate and the AND gate should be connected to a high level (that is, connected to the positive voltage of the power supply through a resistor).

Go to the chapter on the door circuit of the number of electricity. First, the two inputs of the TTL and NAND gates are a triode with two emitters, and the level of the suspended terminal A is clamped by the other input terminal B, because they have the same base C, and the voltage is B+, A=; y=(ab)'=bb)'=b'=(1b)'=b';Therefore, choosing the empty end is equivalent to connecting to the high level.

Generally, when making circuit boards, we use tin to fix the useless feet on the board without connecting to the circuit, that is, to keep it in the air.