The working principle of the D trigger and the status table

SD and RD are connected to the basic RS trigger.

, which are preset and zeroed, and are active low. When SD=1 and RD=0 (SD is not 0, RD is not 1, that is, the level value of the input from the outside of the two control ports respectively, because the low level is valid), regardless of the state of the input terminal D, Q=0 and Q is not =1, that is, the trigger is set to 0.

When sd=0 and rd=1 (sd's non-1, rd's non-0), q=1, q-not=0, the trigger is set to 1, sd and rd are often referred to as direct 1 and 0. Let's set them all high levels.

It does not affect the operation of the circuit.

The d trigger has the function of setting "0" and "1". Here's how the Maintain Blocking D trigger works.

Let q=0 and [d]=1, when cp comes, the flip-flop will be set to "1", and the logic level of each point of the flip-flop is shown in Figure 20-5-2. When performing the set "1" operation, the C gate outputs high; The D gate outputs a low level, and at this time, it should be guaranteed to be set to "1" and "0" should be disabled. To do this, d=0 is added to the input of the C gate through the line to ensure that c=1 is maintained, thus disabling the setting of "0".

At the same time, d=0 is added to the input of the f gate through the line to ensure f=1, and together with cp=1, d=0 is guaranteed, so that the setting "1" is maintained.

The process of setting "0" is similar. Set q=1 and [d]=0, and when cp comes, the trigger will be set to "0". When performing the "0" operation, the C gate output is low, and the "0" should be ensured and the "1" should be disabled.

To do this, c=0 is added to the input of the E gate through the line to ensure that e=1, thus ensuring that c=0 is maintained, and "0" is maintained. At the same time, e=1 is added to the input of the f gate through the line to ensure f=0, so that d=1 is prohibited. The above process is shown in Figure 20-5-3.

The lines or lines in the circuit diagram are added to the same side of the "1" channel or the "0" channel respectively, and play the role of maintaining "1" or "0"; Both the line and the line are added to the other side of the channel, which plays the role of blocking "0" or "1". So the line is called the "0" blocking line, the line is the "1" maintenance line, the line is called the "1" blocking line, and the line is the "0" holding line. From the point of view of circuit structure, it is not difficult to understand the working principle of the circuit as long as the structure of the circuit is clear and the correct analysis method is adopted.

Figure 20-5-3 Flip-flop set to 0 Figure 20-5-4 D flip-flop with asynchronous preset function.

Based on the analysis of the working principle, it can be seen that the sustain blocking D flip-flop starts to flip when the rising edge of the clock comes. We call the edge of the clock that flips the flip-flop an action edge.

Figure 20-5-4 shows a complete circuit diagram of the maintenance blocking D flip-flop with asynchronous zeroing and preset terminals. The direct "0" and "1" functions of this trigger are performed correctly both during periods of low and high levels of the clock.

When no pulse is acting (c=0), the control circuit is blocked, and the flip-flop state remains unchanged regardless of the value of d.

When there is a pulse action (c=1), if d=0, the output of NAND gate G4 is 1, and the output of G3 is 0, and the trigger state is set to 0; If d=1, the NAND gate G4 output is 0 and G3 output is 1, and the trigger state is set to 1i.e. q (n+1) = d

The equation of state for the D flip-flop is: Q*=D, and the equation of state for the JK flip-flop is: Q*=JQ'+k'q。

There are two ways to trigger the d-flip-flop: level trigger and edge trigger. The former can be triggered when cp (clock pulse) is equal to 1, and the latter is triggered mainly in front of cp (forward jump 0 1).

The quadratic state of the D trigger depends on the state before the D trigger, that is, the quadratic state = d, so it has two functions of setting 0 and 1. For the edge D flip-flop, the circuit has the function of staying blocked at Cp=1, so the change in the data state of the D-side does not affect the output state of the flip-flop at Cp=1.

The working process is as follows:

1. When cp=0, it is blocked with the NAND gate G3 and G4, and its output Q3=Q4=1 remains unchanged. At the same time, since the feedback signal from Q3 to Q5 and Q4 to Q6 opens the two gates, the input signal D, Q5=D, Q6=Q5 Non=D Non can be received.

2. When CP changes from 0 to 1, the trigger flips. At this point, G3 and G4 are turned on, and their input states of Q3 and Q4 are determined by the output states of G5 and G6. Q3 = Q5 Non = D Non, Q4 = Q6 Non = D.

From the logic function of the basic rs flip-flop, it can be seen that q=q3 is not =d.

In short, the trigger is to receive the input signal before the CP forward jump, trigger the flip when the positive edge jumps, and the input is blocked after the positive jump, and the three steps are completed after the forward jump, so it is called the edge flip-flop. Compared with the master-slave flip-flop, the edge flip-flop of the same process has stronger anti-interference ability and higher working speed. /span>。

From the logical function of the basic rs flip-flop, it can be seen that q=q3 is not =d.

d trigger. qn+1=d

qn is the present state, and the subordinated state is qn+1, and qn+1 becomes the new qn.

A logical symbol for the edge trigger.

, add a dynamic symbol at the end of C1 - an arrow to indicate that the flip-flop responds only to the rising edge of the clock, and if a circle is added in front of the dynamic symbol, it means that the flip-flop only responds to the falling edge of the clock.

Input D is preceded by a "1", which indicates that this input is subject to clock signals.

, and there is no 1 in front of the set and zero ends s and r, indicating that these two inputs are not affected by the clock signal, that is, they are asynchronous set one and asynchronous zero ends.

Edge d flip-flop.

Input D is input from one latch, the two latches share the clock signal CLK, and the third latch generates a flip-flop state output Q and Q NOT. In addition, there is an asynchronous zero end (RD non) and an asynchronous set side (SD non).

In the logical symbol of the edge flip-flop, a dynamic symbol is added to the C1 end - an arrow indicates that the flip-flop only responds to the rising edge of the clock, and if a circle is added in front of the dynamic symbol, it means that the flip-flop only responds to the falling edge of the clock.

Input D is preceded by a "1", which means that this input is affected by the clock signal, while there is no 1 in front of the set end and the zero end S and R, indicating that these two inputs are not affected by the clock signal, that is, they are asynchronous set one and asynchronous zero end.

d trigger: qn+1=d

<> just check it in the table.

d trigger. It is a storage device that plays the role of temporary data.

The MOS transistor is generally used as a switch in the circuit.

Or and gate.

Flip-flops are memory devices, and different types of flip-flops differ depending on the value of the input data and the scratching data. The D flip-flop is the most versatile because storing data is the input to D. Nowadays, the D flip-flop is the basic component of timing design in digital digital integrated circuits.

When JK triggers.

When the clock pulse action occurs, when J and K are 0 at the same time, the state does not change; When j is 0 and k is 1, the quadratic state is 0; When j is 1 and k is 0, the quadratic state is 1; When j=1k=1, the quadratic state is the opposite of the current state. d trigger (by NAND gate.

composition), and its logical function is as follows: when d=1, q=0;When d=0, q=1;

Second, the trigger method is different:

The JK flip-flop is triggered at the edge of the clock, and generally the rising edge flip-flop can be classified as high.

Flip-flops and low-level flip-flops, sometimes also divided into clock edge flip-flops, are binary with memory capabilities.

Memory device is one of the basic devices of various sequential logic circuits. Triggers can be divided into RS triggers, JK triggers, D triggers, T triggers, etc., and can be divided into two categories: master-slave triggers and edge triggers according to their functions.

At present, the domestic production of TTL integrated triggers mainly includes EDGE-D trigger sail head, EDGE-JK trigger and master-slave JK trigger. These triggers can be converted to other function triggers, but the trigger mode of the converted trigger doesn't change. For example, a trigger for a conversion from an edge is still triggered by an edge.

a) The Q and Q waveforms of the output in the diagram are determined based on the input CP and D terminals. The equation for the d flip-flop is qn+1=d, and the flipping of the q and q waveforms can be obtained sequentially.

The trigger has two steady states, namely "0" and "1", which can be flipped from one steady state to another under the action of certain external signals. The secondary state of the d flip-flop depends on the state of the attitude leak at the front d end of the trigger, i.e., the secondary state = d. Therefore, it has two functions: set 0 and set 1.

2) Principle: When SD and RD are connected to the input terminal of the basic RS flip-flop, which are preset and cleared respectively, and the low level is active:

d=0, cp is the rising edge of the clock, the output q=0, non-q=1;

d=1, cp is the rising edge of the clock, output q=1, non-q=0;

The D-end input is uncertain, cp=0, the Q-end output is unchanged, and the non-Q-end Yumu output is also unchanged;

The D-terminal input is uncertain, CP=1, the Q-terminal output is unchanged, and the non-Q-terminal output is also unchanged.