The principle and function of CD4093BE

Updated on healthy 2024-06-14
9 answers
  1. Anonymous users2024-02-11

    Schmidt triggers.

    The input (and output (10) are reversed, i.e. the input is low and the output is high. And charge the capacitor by R10, and the sleep time increases. The capacitor voltage rises slowly to reach the Schmidt flip level.

    , the output is low, and the parallel circuit formed by R10 and D6 R11 is passed.

    Discharge. It's faster than the charging process. After a short period of time, the capacitor voltage is again below the Schmidt flip level, the output becomes higher again, and the capacitor is charged by R10.

    This cycle constitutes **, according to the duty cycle of the schematic.

    More than 50%. Increasing R10 or decreasing R11 increases the duty cycle.

    The Schmitt trigger has two steady states, but unlike the general flip-flop, the Schmitt trigger adopts the potentiometric trigger mode, and its state is maintained by the input signal potential; For input signals with two different directions of change, negative decrement and forward increment, the Schmitt trigger has different threshold voltages.

  2. Anonymous users2024-02-10

    The CD4093 consists of four 2-input Schmitt trigger circuits. Each circuit is a 2-input NAND gate with a Smitt trigger function at two inputs. Each gate opens and closes at different points on the rising and falling edges of the signal.

    The difference between the rising voltage (VP) t and the falling voltage (V n) is defined as the hysteresis voltage (V t).

    First, the principle. CD4093 Pin Diagram:

    <>2. Role. <>

    The circuit is mainly composed of a four-2 input "and" gate integrated circuit CD4093. R1, C1 and CD4093 an NAND gate (, pin, IC1) constitute a 400Hz square wave oscillator, and the square wave output of the oscillator is divided into two channels: one is directly fed into an NAND gate circuit (, pin, IC2); The other path is fed through capacitor C2 into an NAND gate (, pin, IC3) at an infusion end.

    Since IC2 is connected in the form of an NOT gate, the potential difference between its input and output terminals is 180°, and the signal output of IC2 is coupled to the other input of IC3 through C3 and C4.

    Since the level of the two inputs of IC3 is the same. The phase is reversed, so only IC1 oscillates normally, and at least one of the two inputs of IC3 is low, so the output of IC3 is stable high, and VT1 cuts off due to the effect of C6. However, if the input signal at any of the IC3 inputs is canceled or the signal amplitude is reduced to a level lower than the input start level of the gate, IC3 outputs a square wave signal.

    When there is a conductor close to the induction electrode sheet, it will make the part of the signal that is coupled to the input end of IC3 by C2 be shunted to the ground, if the signal amplitude after being shunted is lower than the threshold level of the non-gate transmission terminal, IC3 will output a square wave signal, and the signal will be made to switch VT1 after rectification by VD1 and VD2, and the power supply of the relay will be turned on to make it engaged.

    Capacitor C4 is a sensitivity adjustment capacitor, if you need the circuit to work at the maximum sensitivity, you can first adjust C4 to make the relay just engage, and then adjust C4 to make the relay just disconnect, and then seal C4 with high-frequency wax or insulating paint.

  3. Anonymous users2024-02-09

    This is a screenshot of the 'infrared proximity switch circuit', D2 is the infrared emitting diode, it must be continuously emitted infrared rays, and then an oscillator can be used to generate a pulse signal to control the conduction and shutdown of the p-type transistor.

    When the power is first started, there is no voltage at both ends of C5, 8 and 9 are low levels on the diagram, and the output of 10 is high, charge C5 through the resistor R10 When the two-point potential rises to the threshold voltage vh of the flip-flop, the 10-point output is low, and the capacitor begins to discharge through the diode and the resistor R11 When the two-point potential drops to the threshold voltage vl of the flip-flop, the 10-point output is high, and the capacitor starts charging. In this way, a periodic high and low level is output at 10 points.

    Advantages: strong anti-interference ability, can obtain stable high and low level signals.

  4. Anonymous users2024-02-08

    With non-gate Schmitt triggers, it assists in vibration and shaping. There is a lot of information, just look it up on the Internet.

  5. Anonymous users2024-02-07

    Dear, do you do infrared automatic control faucet.

  6. Anonymous users2024-02-06

    Simple electronic password lock (1).

  7. Anonymous users2024-02-05

    The initial state of the circuit is in the reset state, and the Q1 and Q2 terminals are low. When the FI signal is input, its output is also controlled by feedback from the Q2 side of the flip-flop IC2 due to the action of the XOR gate at the input (the attached table is the XOR gate logic function table) (the NAND gate F2 is an added first-stage delay gate, and the waveform at point A is the same as that of Q2). Under the action of the rising edge of the first FI clock pulse, the flip-flops IC1 and IC2 are flipped.

    Due to the feedback at Q2, the XOR gate outputs a very narrow positive pulse, the width of which is determined by the delay of the two-stage D flip-flop and the inverting gate. When the first FI pulse jumps down, the XOR gate output jumps up immediately, flipping the IC1 flip-flop again, while the IC2 flip-flop state remains unchanged. This causes the clock pulse end CL1 of the IC1 flip-flop to have a full cycle of input within half a cycle of the first input clock, but in the action of a later input clock, the clock input of the IC1 flip-flop follows the FI signal (inverted or inverted) because the Q2 end of the IC2 flip-flop is high.

    Originally, the IC1 flip-flop can output a full cycle of pulses by inputting two complete input pulses, but now due to the feedback control effect of the XOR gate and the Q2 end of the IC2 flip-flop, a cycle of pulse output is obtained under the action of the first FI pulse, so that every input half-clock pulse is realized, and a complete cycle of output is obtained at the Q1 end of the IC1 flip-flop.

  8. Anonymous users2024-02-04

    CD4069 is a 6 inverter circuit, (NOR gate, 1 input, 1 output) mainly for the role of inverting in digital circuits.

  9. Anonymous users2024-02-03

    CD4069 alarm circuit, although the sound is harsh, it can save lives at critical moments, and the oscilloscope understands.

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