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According to the direction of data transmission, bus operations can be divided into bus read operations and bus write operations. The bus read operation refers to the CPU reading data from the memory or the I-O port, including finger taking, memory reading, and I0 reading, and the interrupt-response operation can also be regarded as a special bus read operation; Bus write operation refers to the operation of the CPU to write data to memory or I.O. port, including memory write, |0 Write T1 state starts in T1 state, the MIO signal is valid, it indicates whether the CPU is going to make a memory access or an IO access. The t1 state is the address state, and the processor sends out the address of the memory or I.O port to be accessed.

The CPU sends a 4-bit higher address through the address status line A19 S6--A1 6 S3, and a lower 1 6-bit address through the address data line AD15--AD0. Since the 20-bit address line of the 8086 is time-multiplexed with the state and data lines, the address signal must be latched in the T1 state. In the T1 state, the CPU's address latch enables the ALE signal to be active, and ALE is a forward pulse that acts on the address latch 8282, and the falling edge of ALE locks the address signal in 8282.

The high-bit data bus enable signal BHE is also a time-sharing multiplexed signal, which is sent through the BHE S7 pin in the T1 state, and the BHE signal is used as the odd address storage option. Usually BHE is latched with an address latch along with a 20-bit address signal, so that their state is valid for the entire bus cycle. In addition, the data transmission direction control signal DT R of the data bus transceiver will also be valid in the T1 state, and since the bus period is a read period, the DT R side outputs a low level to control the data bus transceiver to receive data.

The T2 state is in the T2 state, the address signal ends, and AD15--AD0 enters the high-impedance state to prepare for the data to be read. and A19 S7 - A16 S3 and BHE S7The upper output status information outputs the read signal rd, rd signal to all the memory and i 0 interface chip in the system, and together with the address line, open the memory unit or |The three-state gate of the O port reads data out of the storage unit or O port and sends it to the data bus of the system. At the same time, the data-enable signal DEN goes low, and the control bus transceiver enters an active state.

The T3 state basic bus period is a bus period that does not need to be inserted into the waiting state, and consists of 4 t states. During the base bus cycle, the CPU usually latches the data that appears on the data line on the falling edge of T3. T4 state T4 state is the end of the bus cycle, except for the CPU read and write data, the M IO, address, and data all become high-impedance state, ending the current bus cycle.