MCS 51 MCU Lookup Schedule

16 and 7 are the number of bytes between the PC and the data ** at the time of the lookup command.

mov a ，@r0 ;take the data from the address pointed by r0 to aanl a, 0fh; The high four digits are cleared.

add a,#16 ；Plus 16

movc a， @a+pc ；Look up the table, the first address of the table is the absolute address pc + amovc a, @a + pc needs 1 byte.

The length of the query command from the address at the top of the table is the number of bytes.

Assembler with dptr:

org 0100h

mov 30h,#12h

mov 31h,#34h

mov 32h,#56h

mov 33h,#78h

lcall subrte

org 1000h

subrte: mov r0,#30h ;Set the initial value of the address pointer r0 mov r1, 40h ; set the initial value of the address pointer r1 mov r2, 4 ; Set the number of bytes.

loop: mov a,@r0 ;Take the hexadecimal number anl a, 0fh ; The shield is 4 bits high.

mov dptr,#table ;

movc a,@a+dptr ;Convert the lower 4 digits of the lookup table to ASC code MOV @r1,A; Send the result.

inc r1 ;Modify the pointer.

mov a,@r0 ;Get a new hexadecimal number.

swap a ;The high 4 bits are swapped with the low 4 bits.

anl a,#0fh ;Take 4 digits higher.

add a,#

movc a,@a+pc ;Convert the high 4 digits of the lookup table to the ASC code MOV @r1,A

inc r0

inc r1

djnz r2,loop

dec r1

rettable: db '012345678'

db '9abcdef'end

The length of the lookup command from the address at the top of the table".

Of course, it refers to the "number of bytes", and the length of the "instruction" is inconsistent, and the length of the account is inconsistent. With this method Mova, @r0

anl a，#0fh

add a,#

movc a， @a+pc

Looking up the table is purely asking for trouble for yourself.

Refers to: the number of bytes.

The lookup table method is the most convenient way to get results on the fly.

adda, 16 is to calculate the address offset.

adda,#

It's the same. It is to calculate how much address is offset from the instruction of the lookup table to **.

Note: add

a, start --- here

movca，@a+pc

movr1，aincr0

incr1djnzr2，loopdecr1

The ret ends here, and there are 7 instructions in between, so the offset = 7table:db'012345678'

The structure of the 80C51 interrupt system.

The interrupt system of the 80C51 has 5 interrupt sources (8052 has 6), 2 priority, and can achieve secondary interrupt nesting.

1. (It can be selected by it0 (whether it is active low or falling edge. When the CPU detects a valid interrupt signal on the pin, the interrupt flag IE0 (set to 1) requests an interrupt from the CPU.

2. (It can be selected by IT1( whether it is active low or active on the falling edge.) When the CPU detects a valid interrupt signal on the pin, the interrupt flag IE1 (set 1) to request an interrupt from the CPU.

3. tf0(, the on-chip timing counter t0 overflows the interrupt request flag. When the timing counter T0 overflows, set TF0 and request an interrupt from the CPU.

4. TF1(, the on-chip timing counter T1 overflows the interrupt request flag. When the timing counter T1 overflows, set TF1 and request an interrupt from the CPU.

5. RI (or TI (, serial port interrupt request flag. When the serial port receives a frame of serial data, set the RI or when the serial port sends a frame of serial data, and apply to the CPU for interrupt.

Hope it helps.

Level interruption and edge interruption, the former to ensure that the high level time is more than 4 cycles, the latter is divided into leading edge interruption and rear edge interruption, the steepness of the edge also has requirements, can not be too flat, you can refer to the explanation in the book.

Low level triggering.

Triggered high.

Nothing is required.

Timer interrupts, externally triggered interrupts.

It must be configured first, and the timer interrupt is interrupted when the time comes.

An external trigger interrupt triggers a low-level signal on the corresponding pin, 89C51 is,

MCS-51 has a total of 111 instructions, and the instructions are classified.

1. According to the bytes occupied by the instruction:

1) Single-byte instructions (49 entries) such as MOV A, R2, (machine code 11101010).

2) Double-byte instructions (46 items) such as mov a, 0bh, (machine code 74h, 0bh).

3) Three-byte instructions (16 pieces) such as mov 0bh, 0bh, (machine code 75h, 0bh, 0bh).

2. According to the execution time of the instruction: (1 machine cycle is 12 clock cycles).

1) 1 machine cycle (64 lines), e.g. MOV A, R2 MOV A, 0bh, 2) 2 machine cycles (45 pcs), e.g. MOV 0bh, 0bh

3) 4 machine cycles (2 lines), multiplication and division instructions.

Instruction format. 1. Score according to the opcode and the number of operands.

1. Opcode: It is used to specify what operation the instruction should perform.

Such as MOV A, 0BH, (machine code 74H, 0BH).

where 74h is the opcode, indicating the operation of "sending the immediate number into the ACC";

For example, mov a, 0bh, where 0bh is the operand.

There are single-byte instructions, double-byte instructions, and three-byte instructions of different lengths, and the formats are different: (1) Single-byte instructions: The opcode and operands are in the same byte.

2) Double-byte instructions: opcode + operand.

3) Three-byte instruction: operation loss code + operand + operand.

2. Score according to mnemonics and operands.

Manipulative mnemonic [intent operand, source operand].

Such as mov a, 0bh, (machine code 74h, 0bh), where:

1) MOV is the operation mnemonic, indicating the operation of "internal data transfer";

2) a is the purpose operand, indicating that the "destination register for data transmission" is a;

0bh is the source operand.